PRELIMINARY
CY7C1303BV18
CY7C1306BV18
Document #: 38-05626 Rev. **
Page 4 of 19
Pin Definitions
Name
I/O
Description
D[x:0]
Input-
Synchronous
Data input signals, sampled on the rising edge of K and K clocks during valid Write
operations.
CY7C1303BV18 – D[17:0]
CY7C1306BV18 – D[35:0]
WPS
Input-
Synchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a Write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
BWS0, BWS1,
BWS2, BWS3
Input-
Synchronous
Byte Write Select 0, 1, 2, and 3 - active LOW. Sampled on the rising edge of the K and
K clocks during Write operations. Used to select which byte is written into the device
during the current portion of the Write operations.
CY7C1303BV18 - BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1306BV18 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]
and BWS3 controls D[35:27]
Bytes not written remain unaltered. Deselecting a Byte Write Select will cause the corre-
sponding byte of data to be ignored and not written into the device.
A
Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active Read opera-
tions and on the rising edge of K for Write operations. These address inputs are multi-
plexed for both Read and Write operations. Internally, the device is organized as 1M x
18 (2 arrays each of 512K x 18) for CY7C1303BV18 and 512K x 36 (2 arrays each of
256K x 36) for CY7C1306BV18. Therefore, only 19 address inputs are needed to access
the entire memory array of CY7C1303BV18 and 18 address inputs for CY7C1306BV18.
These inputs are ignored when the appropriate port is deselected.
Q[x:0]
Outputs-
Synchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q[x:0] are automatically three-stated.
CY7C1303BV18 - Q[17:0]
CY7C1306BV18 - Q[35:0]
RPS
Input-
Synchronous
Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically three-stated following the next rising edge of the K clock. Each
Read access consists of a burst of two sequential 18-bit or 36-bit transfers.
C
Input-Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
C
Input-Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read
data from the device. C and C can be used together to deskew the flight times of various
devices on the board cack to the controller. See application example for further details.
K
Input-Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
Input-Clock
Negative Input Clock Input. K is used to capture synchronous inputs to the device and
to drive out data through Q[x:0] when in single clock mode.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is
a resistor connected between ZQ and ground. Alternately, this pin can be connected
directly to VDD, which enables the minimum impedance mode. This pin cannot be
connected directly to GND or left unconnected.
TDO
Output
TDO pin for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC/36M
N/A
Address expansion for 36M. This pin is not connected to the die and so can be tied to
any voltage level on CY7C1303BV18/CY7C1306BV18.
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