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DS14285SN Datasheet(PDF) 8 Page - Dallas Semiconductor |
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DS14285SN Datasheet(HTML) 8 Page - Dallas Semiconductor |
8 / 26 page DS14285/DS14287 8 of 26 RTC ADDRESS MAP The address map of the DS14285/DS14287 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used for control and status. All 128 bytes can be directly written or read except for the following: 1. Registers C and D are read-only. 2. Bit 7 of Register A is read-only. 3. The high order bit of the seconds byte is read-only. The contents of four registers (A,B,C, and D) are described in the “Registers” section. Figure 2. DS14285/DS14287 Address Map TIME, CALENDAR AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate memory bytes. The time, calendar, and alarm are set or initialized by writing the appropriate RAM bytes. The contents of the 10 time, calendar, and alarm bytes can be either Binary or Binary-Coded Decimal (BCD) format. Before writing the internal time, calendar, and alarm registers, the SET bit in Register B should be written to a logic 1 to prevent updates from occurring while access is being attempted. In addition to writing the 10 time, calendar, and alarm registers in a selected format (binary or BCD), the data mode bit (DM) of Register B must be set to the appropriate logic level. All 10 time, calendar, and alarm bytes must use the same data mode. The set bit in Register B should be cleared after the data mode bit has been written to allow the real-time clock to update the time and calendar bytes. Once initialized, the real-time clock makes all updates in the selected mode. The data mode cannot be changed without reinitializing the 10 data bytes. Table 1 shows the binary and BCD formats of the ten time, calendar, and alarm locations. The |
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