DS14285/DS14287

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RESET

RESET

pin can be held low for a time in order to allow the power supply to stabilize. The amount of time

following occurs:

A. Periodic Interrupt Enable (PEI) bit is cleared to 0.

B. Alarm Interrupt Enable (AIE) bit is cleared to 0.

C. Update Ended Interrupt Flag (UF) bit is cleared to 0.

D. Interrupt Request Status Flag (IRQF) bit is cleared to 0.

E. Periodic Interrupt Flag (PF) bit is cleared to 0.

G. Alarm Interrupt Flag (AF) bit is cleared to 0.

J. Update Ended Interrupt Enable (UIE) is cleared to 0.

and out of power fail without affecting any of the control registers.

CEI

Ω resistor.

CEO

CEO

CEO

internal switch to power an external RAM.

DS14285 Only

X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is

designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is

connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1

and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with

ground and that high frequency signals be kept away from the crystal area. For more information on

crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal

Considerations with Dallas Real Time Clocks.”

section for considerations in selecting the size of the external energy source