CY7C1297F
Document #: 38-05429 Rev. *B
Page 3 of 15
Pin Descriptions
Name
TQFP
I/O
Description
A0, A1, A
37,36,32,
33,34,35,
44,45,46,
47,48,80,
81,82,99,100
Input-
Synchronous
Address Inputs used to select one of the 64K address locations. Sampled at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A[1:0] feed the 2-bit counter.
BWA, BWB
93,94
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes
to the SRAM. Sampled on the rising edge of CLK.
GW
88
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global Write is conducted (ALL bytes are written, regardless of the values
on BW[A:B] and BWE).
BWE
87
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a Byte Write.
CLK
89
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
CE1
98
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1
is HIGH.
CE2
97
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3
92
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
86
Input-
Asynchronou
s
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins. OE is masked during the first clock of a
Read cycle when emerging from a deselected state.
ADV
83
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
ADSP
84
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH
ADSC
85
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ
64
Input-
Asynchronou
s
ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal opera-
tion, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs
DQPA, DQPB
58,59,62,
63,68,69,
72,73,8,9,12,
13,18,19,22,
23,74,24
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by the addresses presented during the previous clock
rise of the Read cycle. The direction of the pins is controlled by OE. When OE is
asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are
placed in a three-state condition.
VDD
15,41,65, 91
Power
Supply
Power supply inputs to the core of the device.
VSS
5,10,17,21,
26,40,55,60,
67,71,76,90
Ground
Ground for the device.
VDDQ
4,11,20,27,
54,61,70,77
I/O Power
Supply
Power supply for the I/O circuitry.
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