4-Mbit (512K x 8) Static RAM
CY7C1049CV33
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05006 Rev. *E
Revised March 29, 2005
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
•High speed
—tAA = 10 ns
• Low active power
— 324 mW (max.)
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
Functional Description[1]
The CY7C1049CV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1049CV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Notes:
1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com.
Logic Block Diagram
Pin Configuration
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512K x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
CE
1
2
3
4
5
6
7
8
9
10
11
14
23
24
28
27
26
25
29
32
31
30
Top View
SOJ
12
13
33
36
35
34
16
15
21
22
GND
A1
A2
A3
A4
A5
A6
A7
A8
WE
VCC
A18
A15
A12
A14
I/O5
I/O4
A9
A0
I/O0
I/O1
I/O2
OE
A17
A16
A13
CE
A9
18
17
19
20
GND
I/O7
I/O3
I/O6
VCC
A10
A11
NC
NC
A10
A6
1
2
3
4
5
6
7
8
9
10
11
14
31
32
36
35
34
33
37
40
39
38
Top View
TSOP II
12
13
41
44
43
42
16
15
29
30
VCC
A7
A8
A9
NC
NC
NC
NC
A18
VSS
NC
A15
A0
A3
I/O0
A4
CE
A17
A12
A1
A2
18
17
20
19
I/O1
27
28
25
26
22
21
23
24
NC
VSS
WE
I/O2
I/O3
A5
NC
A16
VCC
OE
I/O7
I/O6
I/O5
I/O4
A14
A13
A11
A10
NC
NC
NC
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