CY7C1041CV33
4-Mbit (256K x 16) Static RAM
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document Number: 38-05134 Rev. *I
Revised February 14, 2008
Features
■ Temperature ranges
❐ Commercial: 0°C to 70°C
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
■ Pin and function compatible with CY7C1041BV33
■ High speed
❐ tAA = 10 ns (Commercial, Industrial and Automotive-A)
❐ tAA = 12 ns (Automotive-E)
■ Low active power
❐ 324 mW (max)
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin
TSOP II and 48-Ball FBGA packages
Functional Description
The CY7C1041CV33 is a high performance CMOS static RAM
organized as 262,144 words by 16 bits.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15)
is written into the location specified on the address pins (A0
through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. For more information, see the Truth
Table on page 9 for a complete description of Read and Write
modes.
The input and output pins (IO0 through IO15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
256K x 16
RAM Array
IO0–IO7
A0
A1
A2
A3
A6
COLUMN DECODER
INPUT BUFFER
OE
A4
A5
IO8–IO15
WE
BLE
BHE
A8
A7
CE
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