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CY7C1061DV33
Document Number: 38-05476 Rev. *D
Page 7 of 11
Figure 4. Read Cycle No. 2 (OE Controlled) [13, 14]
Figure 5. Write Cycle No. 1 (CE Controlled) [15, 16, 17]
Switching Waveforms (continued)
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
tDBE
tLZBE
tHZCE
OE
CE1
ADDRESS
DATA OUT
VCC
SUPPLY
BHE, BLE
CURRENT
CE2
HIGH
IMPEDANCE
ICC
ISB
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
t
DATA IO
ADDRESS
CE
WE
BHE, BLE
Notes
14. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
15. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW.
16. Data IO is high impedance if OE, BHE, and/or BLE = VIH.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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