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DS3182 Datasheet(PDF) 7 Page - Dallas Semiconductor

Part # DS3182
Description  Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS3182 Datasheet(HTML) 7 Page - Dallas Semiconductor

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DS3181/DS3182/DS3183/DS3184
7
12.10.4 Receive G.751 E3 Register Map ....................................................................................................... 291
12.10.5 Transmit G.832 E3 Register Map ...................................................................................................... 297
12.10.6 Receive G.832 E3 Register Map ....................................................................................................... 300
12.10.7 Transmit Clear Channel ..................................................................................................................... 309
12.10.8 Receive Clear Channel ...................................................................................................................... 310
12.11FRACTIONAL DS3/E3 ..................................................................................................................312
12.11.1 Fractional Transmit Side Register Map.............................................................................................. 312
12.11.2 Fractional Receive Side Register Map............................................................................................... 314
12.12DS3/E3 PLCP............................................................................................................................316
12.12.1 Transmit Side PLCP........................................................................................................................... 316
12.12.2 Receive Side PLCP Register Map ..................................................................................................... 320
12.13FIFO REGISTERS........................................................................................................................331
12.13.1 Transmit FIFO Register Map ............................................................................................................. 331
12.13.2 Receive FIFO Register Map .............................................................................................................. 335
12.14CELL/PACKET PROCESSOR .........................................................................................................338
12.14.1 Transmit Cell Processor Register Map .............................................................................................. 338
12.14.2 Receive Cell Processor...................................................................................................................... 345
12.14.3 Transmit Packet Processor Register Map ......................................................................................... 357
12.14.4 Receive Packet Processor Register Map .......................................................................................... 362
13 JTAG INFORMATION
372
13.1 JTAG DESCRIPTION....................................................................................................................372
13.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION.............................................................373
13.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS......................................................................375
13.4 JTAG ID CODES.........................................................................................................................376
13.5 JTAG FUNCTIONAL TIMING..........................................................................................................376
13.6 IO PINS ......................................................................................................................................376
14 PIN ASSIGNMENT
377
15 PACKAGE INFORMATION
380
15.1 400-LEAD TE-PBGA (27MM X 27MM, 1.27MM PITCH) (56-G6003-003) .......................................380
16 PACKAGE THERMAL INFORMATION
381
17 DC ELECTRICAL CHARACTERISTICS
382
18 AC TIMING CHARACTERISTICS
384
18.1 FRACTIONAL PORT CHARACTERISTICS.........................................................................................386
18.2 LINE INTERFACE AC CHARACTERISTICS.......................................................................................386
18.3 MISCELLANEOUS PIN AC CHARACTERISTICS................................................................................387
18.4 OVERHEAD PORT AC CHARACTERISTICS.....................................................................................387
18.5 SYSTEM INTERFACE AC CHARACTERISTICS .................................................................................388
18.6 MICRO INTERFACE AC CHARACTERISTICS ...................................................................................390
18.7 CLAD JITTER CHARACTERISTICS ................................................................................................393
18.8 LIU INTERFACE AC CHARACTERISTICS........................................................................................393
18.8.1 Waveform Templates ......................................................................................................................... 393
18.8.2 LIU Input/Output Characteristics........................................................................................................ 397
18.9 JTAG INTERFACE AC CHARACTERISTICS ....................................................................................399
19 REVISION HISTORY
400


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