CY7C1046B
Document #: 38-05144 Rev. **
Page 3 of 8
AC Test Loads and Waveforms
Switching Characteristics[4] Over the Operating Range
7C1046B-12
7C1046B-15
7C1046B-20
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tpower
VCC(typical) to the first access
[5]
1
11
µs
tRC
Read Cycle Time
12
15
20
ns
tAA
Address to Data Valid
12
15
20
ns
tOHA
Data Hold from Address Change
3
33
ns
tACE
CE LOW to Data Valid
12
15
20
ns
tDOE
OE LOW to Data Valid
67
8
ns
tLZOE
OE LOW to Low Z[7]
0
00
ns
tHZOE
OE HIGH to High Z[6, 7]
67
8
ns
tLZCE
CE LOW to Low Z[7]
3
33
ns
tHZCE
CE HIGH to High Z[6, 7]
67
8
ns
tPU
CE LOW to Power-Up
0
00
ns
tPD
CE HIGH to Power-Down
12
15
20
ns
WRITE CYCLE[8, 9]
tWC
Write Cycle Time
12
15
20
ns
tSCE
CE LOW to Write End
8
10
15
ns
tAW
Address Set-Up to Write End
8
10
15
ns
tHA
Address Hold from Write End
0
00
ns
tSA
Address Set-Up to Write Start
0
00
ns
tPWE
WE Pulse Width
8
10
12
ns
tSD
Data Set-Up to Write End
6
810
ns
tHD
Data Hold from Write End
0
00
ns
tLZWE
WE HIGH to Low Z[7]
3
33
ns
tHZWE
WE LOW to High Z[6, 7]
67
8
ns
Notes:
4.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5.
This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation
is started.
6.
tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8.
The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
9.
The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
1046B–3
1046B–4
90%VCC
10%VCC
Vcc
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
R1 481
Ω
R1 481
Ω
R2
255
Ω
R2
255
Ω
167
Ω
Equivalent to:
VENIN EQUIVALENT
1.73V
THÉ
Rise Time:1 V/ns
Fall Time:1 V/ns
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