CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B
Page 6 of 37
Selection Guide
CY7C0430CV
–133
CY7C0430CV
–100
Unit
fMAX2
133[1]
100
MHz
Max Access Time (Clock to Data)
4.2
5.0
ns
Max Operating Current ICC
750
600
mA
Max Standby Current for ISB1 (All ports TTL Level)
200
150
mA
Max Standby Current for ISB3 (All ports CMOS Level)
15
15
mA
Pin Definitions
Port 1
Port 2
Port 3
Port 4
Description
A0P1–A15P1
A0P2–A15P2
A0P3–A15P3
A0P4–A15P4
Address Input/Output.
I/O0P1–I/O17P1 I/O0P2–I/O17P2 I/O0P3–I/O17P3 I/O0P4–I/O17P4 Data Bus Input/Output.
CLKP1
CLKP2
CLKP3
CLKP4
Clock Input. This input can be free running or strobed.
Maximum clock input rate is fMAX.
LBP1
LBP2
LBP3
LBP4
Lower Byte Select Input. Asserting this signal LOW
enables read and write operations to the lower byte. For
read operations both the LB and OE signals must be
asserted to drive output data on the lower byte of the data
pins.
UBP1
UBP2
UBP3
UBP4
Upper Byte Select Input. Same function as LB, but to the
upper byte.
CE0P1,CE1P1
CE0P2,CE1P2
CE0P3,CE1P3
CE0P4,CE1P4
Chip Enable Input. To select any port, both CE0 AND
CE1 must be asserted to their active states (CE0 ≤ VIL and
CE1 ≥ VIH).
OEP1
OEP2
OEP3
OEP4
Output Enable Input. This signal must be asserted LOW
to enable the I/O data lines during read operations. OE is
asynchronous input.
R/WP1
R/WP2
R/WP3
R/WP4
Read/Write Enable Input. This signal is asserted LOW
to write to the dual port memory array. For read opera-
tions, assert this pin HIGH.
MRST
Master Reset Input. This is one signal for All Ports.
MRST is an asynchronous input. Asserting MRST LOW
performs all of the reset functions as described in the text.
A MRST operation is required at power-up.
CNTRSTP1
CNTRSTP2
CNTRSTP3
CNTRSTP4
Counter Reset Input. Asserting this signal LOW resets
the burst address counter of its respective port to zero.
CNTRST is second to MRST in priority with respect to
counter and mask register operations.
MKLDP1
MKLDP2
MKLDP3
MKLDP4
Mask Register Load Input. Asserting this signal LOW
loads the mask register with the external address
available on the address lines. MKLD operation has
higher priority over CNTLD operation.
CNTLDP1
CNTLDP2
CNTLDP3
CNTLDP4
Counter Load Input. Asserting this signal LOW loads the
burst counter with the external address present on the
address pins.
CNTINCP1
CNTINCP2
CNTINCP3
CNTINCP4
Counter Increment Input. Asserting this signal LOW
increments the burst address counter of its respective port
on each rising edge of CLK.
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