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PRELIMINARY
CY7C185D
Document #: 38-05466 Rev. *C
Page 5 of 10
Write Cycle[9]
tWC
Write Cycle Time
10
12
15
ns
tSCE1
CE1 LOW to Write End
8
10
12
ns
tSCE2
CE2 HIGH to Write End
8
10
12
ns
tAW
Address Set-up to Write End
7
10
12
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
7
10
12
ns
tSD
Data Set-up to Write End
6
7
8
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE LOW to High Z[7]
66
7
ns
tLZWE
WE HIGH to Low Z
3
3
3
ns
Switching Characteristics Over the Operating Range (continued)[6]
Parameter
Description
7C185D-10
7C185D-12
7C185D-15
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min.
Max.
Unit
VDR
VCC for Data Retention
2.0
V
ICCDR
Data Retention Current
Non-L, Com’l / Ind’l
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
3mA
L-Version Only
1.2
mA
tCDR
[4]
Chip Deselect to Data Retention Time
0
ns
tR
[10]
Operation Recovery Time
tRC
ns
Data Retention Waveform
Switching Waveforms
Read Cycle No.1[11,12]
Notes:
9. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All 3 signals must be active to initiate a write and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs.
11. Device is continuously selected. OE, CE1 = VIL. CE2 = VIH.
12. WE is HIGH for read cycle.
4.5V
4.5V
tCDR
VDR > 2V
DATA RETENTION MODE
tR
CE
VCC
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
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