CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Document #: 38-06051 Rev. *C
Page 8 of 20
.
AC Test Loads and Waveforms
3.0V
GND
90%
90%
10%
3ns
3 ns
10%
ALL INPUT PULSES
(a) Normal Load (Load 1)
R1 = 590
Ω
3.3V
OUTPUT
R2 = 435
Ω
C= 30 pF
VTH =1.4V
OUTPUT
C = 30 pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay(Load 2)
R1 = 590
Ω
R2 = 435
Ω
3.3V
OUTPUT
C= 5 pF
RTH = 250Ω
≤
≤
including scope and jig)
(Used for tLZ, tHZ, tHZWE & tLZWE
Switching Characteristics Over the Operating Range[15]
Parameter
Description
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Unit
-20
-25
Min.
Max.
Min.
Max.
READ CYCLE
tRC
Read Cycle Time
20
25
ns
tAA
Address to Data Valid
20
25
ns
tOHA
Output Hold From Address Change
3
3
ns
tACE[16]
CE LOW to Data Valid
20
25
ns
tDOE
OE LOW to Data Valid
12
13
ns
tLZOE[17, 18, 19]
OE Low to Low Z
3
3
ns
tHZOE[17, 18, 19]
OE HIGH to High Z
12
15
ns
tLZCE[17, 18, 19]
CE LOW to Low Z
3
3
ns
tHZCE[17, 18, 19]
CE HIGH to High Z
12
15
ns
tPU[19]
CE LOW to Power-Up
0
0
ns
tPD[19]
CE HIGH to Power-Down
20
25
ns
WRITE CYCLE
tWC
Write Cycle Time
20
25
ns
tSCE[16]
CE LOW to Write End
16
20
ns
tAW
Address Valid to Write End
16
20
ns
tHA
Address Hold From Write End
0
0
ns
tSA[16]
Address Set-Up to Write Start
0
0
ns
tPWE
Write Pulse Width
16
20
ns
tSD
Data Set-Up to Write End
12
15
ns
Notes:
15. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
16. To access RAM, CE=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
17. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
18. Test conditions used are Load 3.
19. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with
Busy waveform.