3.3V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static
CY7C056V
CY7C057V
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-06055 Rev. *B
Revised September 6, 2005
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• 16K x 36 organization (CY7C056V)
• 32K x 36 organization (CY7C057V)
• 0.25-micron CMOS for optimum speed/power
• High-speed access: 12/15/20 ns
• Low operating power
— Active: ICC = 250 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 72 bits or more using
Master/Slave Chip Select when using more than one
device
• On-Chip arbitration logic
• Semaphores included to permit software handshaking
between ports
•INT flag for port-to-port communication
• Byte Select on Left Port
• Bus Matching on Right Port
• Depth Expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 144-Pin TQFP or 172-Ball BGA
• Pb-Free packages available
• Compact packages:
— 144-Pin TQFP (20 x 20 x 1.4 mm)
— 172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)
Notes:
1. A0–A13 for 16K; A0–A14 for 32K devices.
2. BUSY is an output in Master mode and an input in Slave mode.
R/WL
CE0L
CE1L
OEL
I/O
Control
Address
Decode
BUSYL
CEL
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
R/WR
CE0R
CE1R
OER
CER
Logic Block Diagram
A0L–A13/14L
True Dual-Ported
RAM Array
BUSYR
SEMR
INTR
Address
Decode
A0R–A13/14R
[2]
[2]
[1]
[1]
14/15
14/15
14/15
14/15
Left
Port
Control
Logic
I/O18L–I/O26L
9
I/O27L–I/O35L
9
I/O0L–I/O8L
9
I/O9L–I/O17L
9
Right
Port
Control
Logic
I/O
Control
9
9
I/OR
9
9
Bus
Match
9/18/36
BA
BM
SIZE
WA
B0–B3
CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static RAM
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