CY7C139 datasheet(11/16 Pages) CYPRESS

Part #	CY7C139

Description	4K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

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Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

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11 / 16 page

CY7C138

CY7C139

Document #: 38-06037 Rev. *B

Page 11 of 16

Interrupt Timing Diagrams

Notes:

31. tHA depends on which enable pin (CEL or R/WL) is deasserted first.

32. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.

Switching Waveforms (continued)

WRITE FFF

tWC

tHA

READ FFF

tRC

tINR

WRITE FFE

tWC

READ FFE

tINR

tRC

ADDRESSR

CE L

R/W L

INT L

OE L

ADDRESSR

R/W R

CER

INT L

ADDRESSR

CE R

R/W R

INTR

OE R

ADDRESSL

R/W L

CE L

INTR

tINS

tHA

tINS

Left Side Sets INTR:

Right Side Clears INTR:

Right Side Sets INTL:

Left Side Clears INTL:

[31]

[32]

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