3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06051 Rev. *C
Revised June 6, 2005
Features
• True Dual-Ported memory cells which allow
simultaneous access of the same memory location
• 4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
• 4K/8K/16K/32K x 9 organizations
(CY7C0139AV/145AV/016AV/017AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20/25 ns
• Low operating power
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
•INT flag for port-to-port communication
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
• Pb-Free packages available
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
2. A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices; A0–A14 for 32K devices;
3. BUSY is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A0L–A11–14L
CEL
OEL
R/WL
BUSYL
I/O
Control
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
A0L–A11–14L
True Dual-Ported
RAM Array
A0R–A11–14R
CER
OER
R/WR
BUSYR
SEMR
INTR
Address
Decode
A0R–A11–14R
[1]
[1]
[3]
[3]
R/WL
OEL
I/O0L–I/O7/8L
CEL
R/WR
OER
I/O0R–I/O7/8R
CER
12–15
8/9
12–15
8/9
12–15
12–15
[2]
[2]
[2]
[2]
Logic Block Diagram
CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
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