CY7B951
Document Number: 38-02010 Rev. *A
Page 2 of 10
Pin Descriptions
Name
I/O
Description
RIN±
Differential In Receive Input. This line receiver port connects the receive differential serial input data stream to the
internal Receive PLL. This PLL will recover the embedded clock (RCLK±) and data (RSER±) infor-
mation for one of two data rates depending on the state of the MODE pin. These inputs can receive
very low amplitude signals and are compatible with all PECL signaling levels. If the RIN
± inputs are
not being used, connect RIN+ to VCC and RIN– to VSS.
ROUT±
ECL Out
Receive Output. These ECL 100K outputs (+5V referenced) represent the buffered version of the
input data stream (RIN±). This output pair can be used for Receiver input data equalization in copper
based systems, reducing the system impact of data-dependent jitter. All PECL outputs can be
powered down by connecting both outputs to VCC or leaving them both unconnected.
RSER±
ECL Out
Recovered Serial Data. These ECL 100K outputs (+5V referenced) represent the recovered data
from the input data stream (RIN±). This recovered data is aligned with the recovered clock (RCLK±)
with a sampling window compatible with most data processing devices.
RCLK±
ECL Out
Recovered Clock. These ECL 100K outputs (+5V referenced) represent the recovered clock from
the input data stream (RIN±). This recovered clock is used to sample the recovered data (RSER±)
and has timing compatible with most data processing devices. If both the RSER± and the RCLK±
are tied to VCC or left unconnected, the entire Receive PLL will be powered down.
CD
TTL/ECL In
Carrier Detect. This input controls the recovery function of the Receive PLL and can be driven by
the carrier detect output from optical modules or from external transition detection circuitry. When
this input is at an ECL HIGH, the input data stream (RIN±) is recovered normally by the Receive
PLL. When this input is at an ECL LOW, the Receive PLL no longer aligns to RIN±, but instead
aligns with the REFCLK
⋅8 frequency. Also, the Link Fault Indicator (LFI) will transition LOW, and the
recovered data outputs (RSER) will remain LOW regardless of the signal level on the Receive data
stream inputs (RIN). When the CD input is at a TTL LOW, the internal transitions detection circuitry
is disabled.
LFI
TTL Out
Link Fault Indicator. This output indicates the status of the input data stream (RIN±). It is controlled
by three functions: the Carrier Detect (CD) input, the internal Transition Detector, and the Out of
Lock (OOL) detector. The Transition Detector determines if RIN± contains enough transitions to be
accurately recovered by the Receive PLL. The Out of Lock detector determines if RIN± is within the
frequency range of the Receive PLL. When CD is HIGH and RIN± has sufficient transitions and is
within the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at an ECL LOW
or RIN± does not contain sufficient transitions or RIN± is outside the frequency range of the Receive
PLL then the LFI output will be LOW. If CD is at a TTL LOW then the LFI output will only transition
LOW when the frequency of RIN± is outside the range of the Receive PLL.
TSER±
Differential In Transmit Serial Data. This line receiver port connects the transmit differential serial input data stream
to the TOUT transmit buffers. Depending on the state of the LOOP pin, this input port can also be
set up to supply the serial input data stream to the Receive PLL. These inputs can receive very low
amplitude signals and are compatible with all PECL signalling levels. If the TSER± inputs are not
being used, connect TSER+ to VCC and TSER− to VSS.
TOUT±
ECL Out
Transmit Output. These ECL 100K outputs (+5V referenced) represent the buffered version of the
Transmit data stream (TSER±). This Transmit path is used to take weak input signals and rebuffer
them to drive low-impedance copper media.
REFCLK±
Diff/TTL In
Reference Clock. This input is the clock frequency reference for the clock and data recovery Receive
PLL. REFCLK is multiplied internally by eight and sets the approximate center frequency for the
internal Receive PLL to track the incoming bit stream. This input is also multiplied by eight by the
frequency multiplier Transmit PLL to produce the bit rate Transmit Clock (TCLK±). REFCLK can be
connected to either a differential PECL or single-ended TTL frequency source. When either
REFCLK+ or REFCLK
− is at a TTL LOW, the opposite REFCLK signal becomes a TTL level input.
TCLK±
ECL Out
Transmit Clock. These ECL 100K outputs (+5V referenced) provide the bit rate frequency source
for external Transmit data processing devices. This output is synthesized by the Transmit PLL and
is derived by multiplying the REFCLK frequency by eight. When this output is turned off, the entire
Transmit PLL is powered down. All PECL outputs can be powered down by connecting both outputs
to VCC or leaving them both unconnected.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
