CY2SSTV16857
Document #: 38-07443 Rev. *D
Page 4 of 8
VOH
Output Voltage, High
VDD/VDDQ = 2.3V to 2.7V, IOH =
–100
µA, VDD=2.3 to 2.7V
VDD –
0.2
V
VDD/VDDQ = 2.3V, IOH = –16 mA
1.95
IIL
Input Current
Data Inputs
VI = 1.7V or 0.8V, VREF = 1.15V or
1.35V, VDD = 2.7V
±5
µA
VI = 2.7V or 0,VREF = 1.15V or
1.35V, VDD = 2.7V
± 5
µA
VI = 1.7V or 0.8V, VREF = 1.15V or
1.35V, VDD = 3.6V
± 5
µA
VI = 2.7V or 0
± 5
µA
CLK, CLK
VI = 1.7V or 0.8V, VREF = 1.15V or
1.35V
±1
µA
VI = 2.7V or 0, VREF = 1.15V or
1.35V, Vdd = 2.7V
± 1
µA
RESET
VI = VDD or VSS, VDD = 2.7V
± 5
µA
VREF
VI = 1.5V or 1.35V, VDD = 2.7
±5
µA
IIH
Input Current, High
Data inputs only
mA.
IDD
Dynamic Supply Current
VI = 1.7V or 0.8V, IO = 0, VDD =
2.7V
90
mA
VI = 2.7V or 0, IO = 0, VDD = 2.7V
90
mA
Cin
Input pin capacitance
RESET
VI = 1.7V or 0.8V, IO = 0, VDD =
2.7V
3pF
Clock and Data Inputs
2.5
2.7
3.5
pF
Lpin
Pin Inductance
All
2.1
4.5
nH
Table 2. AC Input Electrical Specifications (VDD = 2.5 VDC ± 5%, Temperature = 0°C to +85°C)
Parameter
Description
Condition
VDD = 2.5V ± 0.2V
Unit
Min.
Max.
FIN
Input Clock Frequency
CLK, CLK
200
MHz
PW
Pulse Duration
CLK, CLK HIGH or LOW
3.3
ns
TACT
Differential Inputs Active Time
Data inputs must be LOW after RESET HIGH
22
ns
TINACT
Differential Inputs Inactive Time Data and clock inputs must be held at valid levels (not
floating) after RESET LOW
22
ns
TSET
Set-up Time
Fast slew rate, (see notes 5 and 7), Data before CLK,
CLK
0.75
ns
Slow slew rate, (see notes 6 and 7), Data before CLK,
CLK
0.9
ns
THOLD
Hold Time
Fast slew rate, (see notes 5 and 7), Data after CLK, CLK
0.75
ns
Slow slew rate (see notes 6 and 7), Data after CLK, CLK
0.9
ns
IVpp
Input Voltage, Pk–Pk
360
mV
Notes:
5. For data signal input slew rate > 1 V/ns.
6. For data signal input slew rate > 0.5 V/ns and < 1 V/ns.
7. CLK, CLK signals input slew rates are > 1 V/ns.
Table 1. DC Electrical Specifications (VDD = Temperature = 0°C to +85 °C) (continued)
Parameter
Description
Condition
Min.
Typ.
Max.
Unit
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