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FastEdge™ Series
CY2PP326
Document #: 38-07506 Rev.*D
Page 4 of 9
Notes:
10. 50% duty cycle; standard load; differential operation
11. For 3.3V supplies. Jitter measured differentially using an Agilent 8133A Pulse Generator with an 8500A LeCroy Wavemaster Oscilloscope using at least 10,000
data points
12. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
ECL DC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VEE
Negative Power Supply
–2.5V ± 5%, VCC = 0.0V
–3.3V ± 5%, VCC = 0.0V
–2.625
–3.465
–2.375
–3.135
V
VCMR
Differential cross point voltage[7]
Differential operation
VEE + 1.2
0V
V
VOH
Output High Voltage
IOH = –30 mA[8]
–1.25
–0.7
V
VOL
Output Low Voltage
VEE = –3.3V ± 5%
VEE = –2.5V ± 5%
IOL = –5 mA[8]
–1.995
–1.995
–1.5
–1.3
V
VIH
Input Voltage, High
Single-ended operation
–1.165
–0.880 [9]
V
VIL
Input Voltage, Low
Single-ended operation
–1.945 [9]
–1.625
V
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
VPP
Differential Input Voltage[7]
Differential operation
0.1
1.3
V
FCLK
Input Frequency
50% duty cycle Standard load
–
1.5
GHz
TPD
Propagation Delay CLKA or CLKB to
Output pair
< 1 GHz [10]
–
1200
ps
Vo
Output Voltage (peak-to-peak; see Fig-
ure 2)
< 1 GHz
0.375
–
V
VCMRO
Output Common Voltage Range (typ.)
VCC – 1.425
V
tsk(0)
Output-to-output Skew
660 MHz [10], See Figure 3
–
50
ps
tsk(PP)
Part-to-Part Output Skew
660 MHz [10]
–250
ps
TPER
Output Period Jitter (rms)[11]
660 MHz [10]
–2.8
ps
tsk(P)
Output Pulse Skew[12]
660 MHz [10], See Figure 3
–
75
ps
TR,TF
Output Rise/Fall Time (see Figure 2)
660 MHz 50% duty cycle
Differential 20% to 80%
0.08
0.3
ns
tPDL
Output disable time
T = CLK period
2.5T + TPD
3.5T + TPD
ns
tPLD
Output enable time
T = CLK period
3.0T + TPD
4.0T + TPD
ns
CL K 0 /0 #
Ba n k A
B ank B
CL K 0 /0 #
CL K 1 /1 #
CL K 1 /1 #
CL K 0 /0 #
Ba n k A
Ba n k B
Ba n k A
Ba n k B
SE L 0 /1
CL K 0 /0 #
CL K 1 /1 #
Ba n k B
Ba n k A
SE L 0 /1
SEL 0 /1
Ro u t e r O p t io n s
S p lit te r O p tio n s
SEL 0 /1
CL K 1 /1 #
Sw i t c h
S p lit t e r A
R e p eat er
S p l i tte r B
Figure 1. Channel Cross Point Switch/Mux Configurations
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