9

AT24C128/256

0670K–SEEPR–7/03

Device

Addressing

The 128K/256K EEPROM requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (refer to Figure 1). The device address word con-

sists of a mandatory one, zero sequence for the first five most significant bits as shown. This is

common to all 2-wire EEPROM devices.

The 128K/256K uses the two device address bits A1, A0 to allow as many as four devices on

the same bus. These bits must compare to their corresponding hardwired input pins. The A1

and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the

pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read operation is

initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is not

made, the device will return to a standby state.

DATA SECURITY: The AT24C128/256 has a hardware data protection scheme that allows the

Write

Operations

BYTE WRITE: A write operation requires two 8-bit data word addresses following the device

address word and acknowledgment. Upon receipt of this address, the EEPROM will again

respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit

data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,

then must terminate the write sequence with a stop condition. At this time the EEPROM enters

this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2).

PAGE WRITE: The 128K/256K EEPROM is capable of 64-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not send a

stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges

receipt of the first data word, the microcontroller can transmit up to 63 more data words. The

EEPROM will respond with a zero after each data word received. The microcontroller must ter-

minate the page write sequence with a stop condition (refer to Figure 3).

The data word address lower 6 bits are internally incremented following the receipt of each

data word. The higher data word address bits are not incremented, retaining the memory page

row location. When the word address, internally generated, reaches the page boundary, the

following byte is placed at the beginning of the same page. If more than 64 data words are

transmitted to the EEPROM, the data word address will “roll over” and previous data will be

overwritten. The address “roll over” during write is from the last byte of the current page to the

first byte of the same page.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a

start condition followed by the device address word. The read/write bit is representative of the

operation desired. Only if the internal write cycle has completed will the EEPROM respond

with a zero, allowing the read or write sequence to continue.