C9530
Document #: 38-07033 Rev. *C
Page 3 of 11
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required.
Data Protocol
The clock driver serial protocol accepts block write a opera-
tions from the controller. The bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. The C9530 does not support the Block Read
function.
The block write protocol is outlined in Table 2. The addresses
are listed in Table 3.
Serial Control Registers
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
Description
1Start
2:8
Slave address – 7 bits
9
Write = 0
10
Acknowledge from slave
11:18
Command Code – 8 bits
‘00000000’ stands for block operation
19
Acknowledge from slave
20:27
Byte Count – 8 bits
28
Acknowledge from slave
29:36
Data byte 1 – 8 bits
37
Acknowledge from slave
38:45
Data byte 2 – 8 bits
46
Acknowledge from slave
....
......................
....
Data Byte (N–1) – 8 bits
....
Acknowledge from slave
....
Data Byte N – 8 bits
....
Acknowledge from slave
....
Stop
Table 3. SMBus Address Selection Table
SMBus Address of the Device
IA0 Bit (Pin 10)
IA1 Bit (Pin 11)
IA2 Bit (Pin 12)
DE
0
0
0
DC
1
0
0
DA
0
1
0
D8
1
1
0
D6
0
0
1
D4
1
0
1
D0
0
1
1
D2
1
1
1
Byte 0: Function Select Register
Bit
@Pup
Name
Description
7
1
TESTEN
Test Mode Enable.
1 = Normal operation, 0 = Test mode
6
0
SSEN
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to
a 0) 0 = OFF, 1= ON
5
1
SSSEL
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification
4
0
S1
SB1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
3
0
S0
SB0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
2
0
SA1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0)
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