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X28HC256J-12 Datasheet(PDF) 8 Page - Intersil Corporation |
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X28HC256J-12 Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 20 page  8 FN8108.2 May 7, 2007 Software Algorithm Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. Software Data Protection Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28HC256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28HC256 will be write protected during power-down and after any subsequent power-up. Note: Once initiated, the sequence of write operations should not be interrupted. CE WE (VCC) WRITE PROTECTED VCC 0V DATA ADDRESS AAA 5555 55 2AAA A0 5555 ≤tBLC MAX WRITES OK BYTE OR AGE tWC FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE WRITE LAST WRITE DATA XX TO ANY WRITE DATA A0 TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA AA TO ADDRESS 5555 AFTER tWC RE-ENTERS DATA PROTECTED STATE BYTE TO LAST ADDRESS ADDRESS OPTIONAL BYTE/PAGE LOAD OPERATION BYTE/PAGE LOAD ENABLED FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA X28HC256 |
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