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L9347PD Datasheet(PDF) 9 Page - STMicroelectronics |
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L9347PD Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 21 page 9/21 L9347 The ON period of the input signal is measured with a 1MHz clock, synchronized with the external 250kHz clock. For requested precision of the output current the ratio between the frequencies of the input signal and the ex- ternal 250kHz clock has to be fixed according to the graph shown in Fig. Figure 4. Current accuracy according to the input and clock frequency ratio The theoretical error is zero for fCLK / fIN = 125. If the period of the input signal is longer than 132 times the period of the clock the regulator is switched off. For a clock frequency lower than 100kHz the clock control will also disable the regulator. For high precision appli- cations the clock frequency and the input frequency have to be correlated. The output current is measured during the recirculation of the load. The current sense resistor is in series to the free wheeling diode. If this recirculation path is interrupted the regulator stops immediately and the status output remains low for the rest of the input cycle. The output period is 64 times the clock period. With a clock frequency of 250kHz the output PWM frequency is 3.9kHz. The output PWM is synchronized with the first negative edge of the input signal. After that the output and the input are asynchronous. The first period is used to measure the current. This means the first turn-on of the power is 256 µs after the first negative edge of the input signal. As regulator a digital PI-regulator with the Transfer function for: KI: and KP: 0.96 for a sampling time of 256us is realised. To speed up the current settling time the regulator output is locked to 90% output PWM untill the target current value is reached. This happens alsowhen the target current value changes and the output PWM reaches 90% during the regulation. The status output gets low if the target current value is not reached within the regulation error delay time of tRE=10ms. The output PWM is than out of the regulation range from 10% to 90%. 1.5 Protective Circuits The outputs are protected against current overload, overtemperature, and power-GND-loss. The external clock is monitored by a clock watchdog. This clock watchdog detects a minimal frequency fCLK,min and wrong clock duty cycles. The allowed clock duty cycle range is 45% to 55%. The current-regulator stages are protected -10% 5.6% 112.5 132 125 fCLK / fIN 0% Regulator switched off 0.126 z1 – --------------- |
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