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ISL98001 Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL98001 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 31 page 6 FN6148.4 August 20, 2007 tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA IN SDA OUT tF tLOW tBUF tAA tR FIGURE 1. 2-WIRE INTERFACE TIMING Pixel Data DATACLK t HOLD t SETUP DATACLK FIGURE 2. DATA OUTPUT SETUP AND HOLD TIMING Programmable Width and Polarity Analog Video In P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 0 P 9 D 0 R P/GP/BP[7:0] HS OUT 8 DATACLK Pipeline Latency R S/GS/BS[7:0] P 10 P 11 P 12 D 1 D 2 D 3 HSYNC IN The HSYNC edge (programmable leading or trailing) that the DPLL is locked to. The sampling phase setting determines its relative position to the rest of the AFE’s output signals DATACLK t HSYNCin-to-HSout = 7.5ns + (PHASE/64 +8.5)*tPIXEL FIGURE 3. 24-BIT OUTPUT MODE ISL98001 |
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