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X28HC256 Datasheet(PDF) 4 Page - Intersil Corporation |
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X28HC256 Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 20 page  4 FN8108.2 May 7, 2007 Pinouts Pin Descriptions Addresses (A0 to A14) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers, and is used to initiate read operations. Data In/Data Out (I/O0 to I/O7) Data is written to or read from the X28HC256 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28HC256. X28HC256 (28 LD CERDIP, FLATPACK, PDIP, SOIC) TOP VIEW X28HC256 (32 LD PLCC, LCC) TOP VIEW X28HC256 (28 LD PGA) BOTTOM VIEW A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 X28HC256 A6 A5 A4 A3 A2 A1 A0 NC I/O0 A8 A9 A11 NC OE A10 CE I/O7 I/O6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 X28HC256 11 I/O0 10 A0 14 VSS 9 A1 8 A2 7 A3 6 A4 5 A5 2 A12 28 VCC 12 I/O1 13 I/O2 15 I/O3 4 A6 3 A7 1 16 I/O4 20 CE 22 OE 24 A9 17 I/O5 27 WE 19 I/O7 21 A10 23 A11 25 A8 18 I/O6 26 A13 A14 X28HC256 X28HC256 |
Similar Part No. - X28HC256_07 |
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Similar Description - X28HC256_07 |
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