Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t

HZD

TRI-STATE Delay

Figure 7 (Note 4)

R

Ω,

C

2.3

10

ns

t

LZD

TRI-STATE Delay

1.9

10

ns

t

ZHD

HIGH Delay

1.0

10

ns

t

ZLD

LOW Delay

1.0

10

ns

t

SPW

SYNC Pulse Width

Figure 9,

R

Ω

5*t

TCP

6*t

TCP

ns

t

PLD

Serializer PLL Lock Time

Figure 8,

R

Ω

510*t

TCP

1024*t

TCP

ns

t

SD

Serializer Delay

Figure 10 ,R

Ω

t

t

t

ns

t

RJIT

Random Jitter

Room Temp., 3.3V,

66 MHz

4.5

ps

(RMS)

t

DJIT

Deterministic Jitter

Figure 16, (Note 8)

15 MHz

-430

190

ps

66 MHz

-40

70

ps

Deserializer Timing Requirements for REFCLK

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

t

RFCP

REFCLK Period

15.2

T

66.7

ns

t

RFDC

REFCLK Duty Cycle

40

50

60

%

t

t

TCP

Ratio of REFCLK to

TCLK

0.95

1.05

t

RFTT

REFCLK Transition Time

6ns

Deserializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol

Parameter

Conditions

Pin/Freq.

Min

Typ

Max

Units

t

RCP

Receiver out Clock

Period

t

RCLK

15.2

66.7

ns

t

RDC

RCLK Duty Cycle

RCLK

45

50

55

%

t

CLH

CMOS/TTL

Low-to-High

Transition Time

CL=15pF

Figure 4

ROUT(0-17),

LOCK,

RCLK

2.2

4

ns

t

CHL

CMOS/TTL

High-to-Low

Transition Time

2.2

4

ns

t

ROS

ROUT (0-9) Setup

Data to RCLK

Figure 12

0.35*t

RCP

0.5*t

RCP

ns

t

ROH

ROUT (0-9) Hold

Data to RCLK

−0.35*t

RCP

−0.5*t

RCP

ns

www.national.com

4