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X96011V14I Datasheet(PDF) 4 Page - Intersil Corporation |
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X96011V14I Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 18 page 4 FN8215.2 February 25, 2008 D/A Converter Characteristics (See pg. 5 for standard conditions) SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IFS Iout Full Scale Current DAC input Byte = FFh, Source or sink mode, V(IOUT) is VCC -1.2V in source mode and 1.2V in sink mode. (Notes 5, 6 ) 1.56 1.58 1.6 mA OffsetDAC Iout D/a Converter Offset Error 1 1 LSB FSErrorDAC Iout D/a Converter Full Scale Error -2 2 LSB DNLDAC Iout D/a Converter Differential Nonlinearity -0.5 0.5 LSB INLDAC Iout D/a Converter Integral Nonlinearity With Respect To A Straight Line Through 0 And The Full Scale Value -1 1 LSB VISink I1 Sink Voltage Compliance In this range the current at I1 vary < 1% 1.2 VCC V VISource I1 Source Voltage Compliance In this range the current at I1 vary < 1% 0 VCC - 1.2 V IOVER I1 Overshoot On D/a Converter Data Byte Transition DAC input byte changing from 00h to FFh and vice versa, V(I1) is VCC - 1.2V in source mode and 1.2V in sink mode. (Note 7) 0µA IUNDER I1 Undershoot On D/a Converter Data Byte Transition 0µA trDAC I1 Rise Time On D/a Converter Data Byte Transition; 10% To 90% 530 µs TCOI1I2 Temperature Coefficient Of Output Current Iout See Figure 5 ±200 ppm/°C NOTES: 5. LSB is defined as divided by the resistance between R1 or R2 to Vss. 6. OffsetDAC: The Offset of a DAC is defined as the deviation between the measured and ideal output, when the DAC input is 01h. It is expressed in LSB. FSErrorDAC: The Full Scale Error of a DAC is defined as the deviation between the measured and ideal output, when the input is FFh. It is expressed in LSB. The OffsetDAC is subtracted from the measured value before calculating FSErrorDAC. DNLDAC: The Differential Non-Linearity of a DAC is defined as the deviation between the measured and ideal incremental change in the output of the DAC, when the input changes by one code step. It is expressed in LSB. The measured values are adjusted for Offset and Full Scale Error before calculating DNLDAC. INLDAC: The Integral Non-Linearity of a DAC is defined as the deviation between the measured and ideal transfer curves, after adjusting the measured transfer curve for Offset and Full Scale Error. It is expressed in LSB. 7. These parameters are periodically sampled and not 100% tested. 2 3 V(VRef) 255 x [] 2-Wire Interface AC Characteristics SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS fSCL Scl Clock Frequency See Table 2-Wire Interface Test Conditions on page 5 (Figure 1, 2 and 3) 1 (Note 10) 400 kHz tIN (Note 11) Pulse Width Suppression Time At Inputs 50 ns tAA (Note 11) Scl Low To Sda Data Out Valid 900 ns tBUF (Note 11) Time The Bus Free Before Start Of New Transmission 1300 ns tLOW Clock Low Time 1.3 1200 (Note 10) µs tHIGH Clock High Time 0.6 1200 (Note 10) µs tSU:STA Start Condition Setup Time 600 ns tHD:STA Start Condition Hold Time 600 ns X96011 |
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