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CY7C344
CY7C344B
9
Typical Internal Switching Characteristics Over Operating Range[7]
7C344B–10
7C344B–12
7C344–15
7C344B–15
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tIN
Dedicated Input Pad and Buffer Delay
Com’l/Ind
2
2.5
4
ns
Mil
2.5
4
tIO
I/O Input Pad and Buffer Delay
Com’l/Ind
2
2.5
4
ns
Mil
2.5
4
tEXP
Expander Array Delay
Com’l/Ind
6
68
ns
Mil
68
tLAD
Logic Array Data Delay
Com’l/Ind
5
67
ns
Mil
67
tLAC
Logic Array Control Delay
Com’l/Ind
5
55
ns
Mil
55
tOD
Output Buffer and Pad Delay
Com’l/Ind
3
34
ns
Mil
34
tZX
Output Buffer Enable Delay[27]
Com’l /Ind
5
57
ns
Mil
57
tXZ
Output Buffer Disable Delay
Com’l/Ind
5
57
ns
Mil
57
tRSU
Register Set-Up Time Relative to Clock Signal
at Register
Com’l/Ind
2
2
5ns
Mil
2
5
tRH
Register Hold Time Relative to Clock Signal at
Register
Com’l/Ind
4
5
7ns
Mil
5
7
tLATCH
Flow-Through Latch Delay
Com’l/Ind
0.5
0.5
1
ns
Mil
0.5
1
tRD
Register Delay
Com’l/Ind
0.5
0.5
1
ns
Mil
0.5
1
tCOMB
Transparent Mode Delay[28]
Com’l/Ind
0.5
0.5
1
ns
Mil
0.5
1
tCH
Clock HIGH Time
Com’l/Ind
3
4
6ns
Mil
4
6
tCL
Clock LOW Time
Com’l/Ind
3
4
6ns
Mil
4
6
tIC
Asynchronous Clock Logic Delay
Com’l/Ind
5
67
ns
Mil
67
tICS
Synchronous Clock Delay
Com’l/Ind
0.5
0.5
1
ns
Mil
0.5
1
tFD
Feedback Delay
Com’l/Ind
1
11
ns
Mil
11
tPRE
Asynchronous Register Preset Time
Com’l/Ind
2
35
ns
Mil
35
tCLR
Asynchronous Register Clear Time
Com’l/Ind
2
35
ns
Mil
35
tPCW
Asynchronous Preset and Clear Pulse Width
Com’l/Ind
2
3
5ns
Mil
3
5
tPCR
Asynchronous Preset and Clear Recovery Time Com’l/Ind
2
3
5ns
Mil
3
5
Shaded area contains preliminary information.
Notes:
27. Sample tested only for an output change of 500 mV.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combi-
natorial operation.
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