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Kentron Technologies, Inc. (978) 988-9100
Page 2
Rev. 4/02
64M X 64 UNBUFFERED SDRAM SODIMM
Operating Features:
The SDRAM SODIMM utilizes a clock input for the synchronization. Each operation of the
SDRAM is determined by commands and all operations are referenced to a positive clock edge.
CAS Latency defines the delay from when a Read Command is registered on a rising clock
edge to when the data from the Read Command becomes available at the outputs. The CAS
latency is expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock
cycles.
The burst mode is a very high-speed access mode utilizing an internal column address
generator. Once a column address for the first access is set, following addresses are
automatically generated by the internal column address counter.
All control and address signals are supplied from the chipset through an unbuffered path to the
SDRAMs. There are two clock signals supplied by the motherboard to synchronize the
SODIMM.
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