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ISL5216KI-1Z Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL5216KI-1Z Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 65 page 10 FN6013.3 July 13, 2007 Level Detector An input level detector is provided to monitor the signal level on any of the input busses. The input bus, input format, and the level detection type are programmable (see Microprocessor Interface , GWA registers F804h, F805h and F806h). This signal level represents the wideband signal from the A/D and is useful for controlling gain/attenuation blocks ahead of the converter. The supported monitoring modes include integrated magnitude (like the HSP50214 w/o the threshold) and leaky integration (Yn =Xn xA +Yn-1 x (1-A)) where A = 1, 2 -8, 2-12, or 2-16 (see GWA = F805h). The measurement interval can be programmed from 2 to 65537 samples (or continuous for the leaky integrator case). The output is 32 bits and is read via the μP interface. Note that the accumulators in the input level detector are 32 bits wide. This may limit the integration range to as few as 512 samples (for a 42dB exponent range). 15-BIT MODE: 15-BIT MANTISSA (15:1), 2-BIT EXPONENT (-1, 0), 18dB MAXIMUM EXPONENT RANGE (Note 12) EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING 000 0 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2X1 0 001 6 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2X1 0 010 12 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 0 011 18 X15 X14 X13 X12 X11 X10 X9 X8 X7X6X5X4X3X2X1 0 NOTE: 12. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 1, 1, 0 and 0 respectively. 16-BIT MODE: 16-BIT MANTISSA (15:0), 1-BIT EXPONENT (-1), 6dB MAXIMUM EXPONENT RANGE (Note 13) EXPONENT GAIN (dB) PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING X(-1) = 0 0 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 X(-1) = 1 6 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 NOTE: 13. To select this mode, set IWA *000H/GWA F804H bits 17, 16, 8 and 7 to 1, 1, 0 and 1 respectively. FIGURE 1. INTEGRATED MODE ABSOLUTE VALUE 16 20, -8, -12, -16 32 MSB Σ R E G A B A > B 32 20, -8, -12, -16 EN FIGURE 2. PEAK DETECTOR (See “Errata” on page 63) 16 EN FIGURE 3. LEAKY INTEGRATOR Σ R E G 32 16 X Y 20, -8, -12, -16 A = YN = A * X + (1 - A) * YN-1 ISL5216 |
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