11

FN7450.4

May 9, 2007

Decoding is based on the EL4543 encoding scheme, as

described in Figure 27 and Table 1. The scheme is a three-

level system, which has been designed such that the sum of

the common mode voltages results in a fixed average DC

level with no AC content. This eliminates the effect of EMI

radiation into the common mode signals along the twisted

pairs of the cable.

The common mode voltages are initially extracted by the

EL9111 from the three input pairs. These are then passed to

an internal logic decoding block to provide Horizontal and

FIGURE 27. H AND V SYNCS ENCODED

Sync Ref

The Sync Ref pin is the reference level for the logic low of the

sync outputs. It can be tied to 0V or -5V, but for typical

operation, the Sync Ref pin would tie to 0V. The Sync output

with a 10V single supply and Sync Ref at ground will cause the

This is too large a voltage for logic inputs, so an output voltage

divider of 1k

Ω series from the outputs with 1kΩ to ground will

reduce the output logic levels to 0V and 5V. Different logic

levels may require different output divider ratios.

The Sync Ref is intended to sink all the switching currents as

transitions to logic low are made. This prevents switching

signals crosstalk to the main chip 0V line, as well as adding the

flexibility of referencing to -5V. Thus, the logic output buffer

does use Sync Ref as its negative supply. The Sync Ref pin is

connected to the analog -5V or analog ground as needed and

is a separate pin to prevent noise coupling in the chip.

EL9111 with Single Ended Coax Input

The EL9111 is designed to use twisted pair cat 5 cable input

with sync encoded as differential CMV on the RGB pairs.

Coax cable inputs may be used with a few changes and

limitations. Coax cable cannot have sync encoded as CMV,

so the coax shields are grounded along with the EL9111

RGB minus inputs. The coax center conductor is terminated

with 75

Ω and connected to the RGB plus inputs. The result

is half the video signal will be seen as CMV by the sync

decoding circuit that decodes the video as sync. This causes

noise on the RGB outputs. The noise may be eliminated by

TABLE 1. H AND V SYNC DECODING

RED CM

GREEN CM

BLUE CM

Mid

High

Low

Low

Low

High

Low

Mid

Low

High

Low

High

Mid

High

Low

Mid

Low

High

High

High

NOTE: Level ‘Mid’ is halfway between ‘High’ and ‘Low’

TIME (0.5ms/DIV)

BLUE CM

OUT (CH A)

GREEN CM

OUT (CH B)

RED CM

OUT (CH C)

EL9111, EL9112