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L6569 L6569A

Bootstrap Function

The L6569 has an internal Bootstrap structure that enables the user to avoid the external diode needed, in sim-

ilar devices, to perform the charge of the bootstrap capacitor that, in turns, provide an appropriate driving to the

Upper External Mosfet.

The operation is achieved with an unique structure (patented) that uses a High Voltage Lateral DMOS driven

by an internal charge pump (see Block Diagram) and synchronized, with a 50 nsec delay, with the Low Side

Gate driver (LVG pin), actually working as a synchronous rectifier .

The charging path for the Bootstrap capacitor is closed via the Lower External Mosfet that is driven ON (i.e. LVG

High) for a time interval:

(typical value).

In the L6569A a different start up procedure is followed (see waveform Diagram). The Lower External Mosfet is

Being the LDMOS used to implement the bootstrap operation a ”bi-directional” switch the current flowing into

the BOOT pin (pin 8) can lead an undue stress to the LDMOS itself if a ZERO VOLTAGE SWITCHING opera-

tions is not ensured, and then an high voltage is applied to the BOOT pin. This condition can occur, for example,

when the load is removed and an high resistive value is placed in series with the gate of the external Power

Mos. To help the user to secure his design a SAFE OPERATING AREA for the Bootstrap LDMOS is provided

(fig. 7).

Let’s consider the steps that should be taken.

1) Calculate the Turn on delay ( td ) of your Lower Power MOS:

2) Calculate the Fall time ( tf ) of your Lower Power MOS:

where:

3) Sketch the VBOOT waveform (using log-log scales) starting from the Drain Voltage of the Lower Power MOS

(remember to add the Vs, your Low Voltage Supply, value) on the Bootstrap LDMOS SOA . On fig. 8 an example

is given where:

tion.

t

d

R

g

R

id

+

() C

iss

1

1

V

TH

V

S

-----------

–

--------------------

ln

⋅⋅

=

t

f

R

g

R

id

+

V

S

V

TH

–

------------------------ Q

gd

⋅

=