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DS90CR218AMTD Datasheet(PDF) 4 Page - National Semiconductor (TI) |
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DS90CR218AMTD Datasheet(HTML) 4 Page - National Semiconductor (TI) |
4 / 11 page Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter Min Typ Max Units CLHT CMOS/TTL Low-to-High Transition Time (Figure 2) 2.0 3.5 ns CHLT CMOS/TTL High-to-Low Transition Time (Figure 2) 1.8 3.5 ns RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 8) f = 85 MHz 0.49 0.84 1.19 ns RSPos1 Receiver Input Strobe Position for Bit 1 2.17 2.52 2.87 ns RSPos2 Receiver Input Strobe Position for Bit 2 3.85 4.20 4.55 ns RSPos3 Receiver Input Strobe Position for Bit 3 5.53 5.88 6.23 ns RSPos4 Receiver Input Strobe Position for Bit 4 7.21 7.56 7.91 ns RSPos5 Receiver Input Strobe Position for Bit 5 8.89 9.24 9.59 ns RSPos6 Receiver Input Strobe Position for Bit 6 10.57 10.92 11.27 ns RSKM RxIN Skew Margin (Note 4) (Figure 9) f = 85 MHz 0.49 ns f = 12MHz 2.01 ns RCOP RxCLK OUT Period (Figure 3) 11.76 T 83.33 ns RCOH RxCLK OUT High Time (Figure 3) f = 85 MHz 4 5 6.5 ns RCOL RxCLK OUT Low Time (Figure 3) 3.5 5 6 ns RSRC RxOUT Setup to RxCLK OUT (Figure 3) 3.5 ns RHRC RxOUT Hold to RxCLK OUT (Figure 3) 3.5 ns RCCD RxCLK IN to RxCLK OUT Delay @ 25˚C, V CC = 3.3V (Note 5)(Figure 4) 5.5 7 9.5 ns RPLLS Receiver Phase Lock Loop Set (Figure 5)10 ms RPDD Receiver Powerdown Delay (Figure 7)1 µs Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the receiver input setup and hold time (internal data sampling window). This margin do not take into account the Transmitter Pulse Position (TPPOS) variance and is measured using the ideal TPPOS. This margin allows LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and source clock jitter less than 250 ps. Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency for the 217/287 transmitter and 218A/288A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. AC Timing Diagrams 10108002 FIGURE 1. “Worst Case” Test Pattern www.national.com 4 |
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