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DS36C200I Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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DS36C200I Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 11 page  Application Information (Continued) Transmit Mode Input(s) Input/Output DE RE* DI DO+ DO− HH L L H H HHH L HH 2 > & > 0.8 X X Input(s) Input/Output DE RE* DI DO+ DO− LH X Z Z H = Logic high level L = Logic low level X = Indeterminate state Z = High impedance state TABLE 1. Device Pin Descriptions Pin # M14A Package Pin # MTC14 Package Name (In mode only) Mode Description 3 3 DE Transmit Driver Enable: When asserted low driver is disabled. And when asserted high driver is enabled. 1, 7 1, 7 DI1, DI2 TTL/CMOS driver input pins 10, 13 11, 14 DO2+, DO1+ Non-inverting driver output pin 11, 12 12, 13 DO2−, DO1– Inverting driver output pin 4 4 RE* Receive Receiver Enable: When asserted low receiver is enabled. And when asserted high receiver is disabled. 1, 7 1, 7 RO1, RO2 Receiver output pin 10, 13 11,14 RI2+, RI1+ Positive receiver input pin 11, 12 12, 13 RI2−, RI1– Negative receiver input pin 5 5 Gnd Transmit and Ground pin 22 V CC Receive Positive power supply pin, +5V ± 10% 6, 8, 9, 14 6, 8, 9, 10 NC No Connect IEEE 1394 The DS36C200I drives and receives IEEE 1394 physical layer signal levels. The current mode driver is capable of driving a 55 Ω load with V OD between 172 mV and 285 mV. The DS36C200I is not designed to work with a link layer controller IC requiring full 1394 physical layer compliancy to the standard. No clock generator, no arbitration, and no encode/decode logic is provided with this device. For a 1394 link where speed sensing, bus arbitration, and other func- tions are not required, a controller and the DS36C200I will provide a cost effective, high speed dedicated link. This is shown in Figure 10. In applications that require fully compli- ant 1394 protocol, a link layer controller and physical layer controller will be required as shown in Figure 10. The physi- cal layer controller supports up to three DS36C200I devices (not shown). The DS36C200I drivers are current mode drivers and in- tended to work with two 110 Ω termination resistors in parallel with each other. The termination resistors should match the characteristic impedance of the transmission media. The drivers are current mode devices therefore the resistors are required. Both resistors are required for half duplex opera- tion and should be placed as close to the DO/RI+ and DO/RI− pins as possible at opposite ends of the bus. How- ever, if your application only requires simplex operation, only one termination resistor is required. In addition, note the voltage levels will vary from those in the datasheet due to different loading. Also, AC or unterminated configurations are not used with this device. Multiple node configurations are possible as long as transmission line effects are taken into account. Discontinuities are caused by mid-bus stubs, connectors, and devices that affect signal integrity. The differential line driver is a balanced current source de- sign. A current mode driver, generally speaking has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The typical output current is mere 3.8 mA, a minimum of 3.1 mA, and a maximum of 5.2 mA. The current mode requires that a resistive termination be employed to termi- nate the signal and to complete the loop as shown in Figure 11. The 3.8 mA loop current will develop a differential voltage of 210 mV across the 55 Ω termination resistor which the receiver detects with a 110 mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (210 mV – 100 mV = 110 mV)). The signal is centered around +1.2V (Driver Offset, V OS) with respect to ground as shown in Figure 7. The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quies- cent current remains relatively flat versus switching fre- quency. Whereas the RS-422 voltage mode driver increases exponentially in most case between 20 MHz–50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static I CC requirements of the ECL/PECL designs. LVDS requires > 80% less current than similar PECL devices. AC specifi- cations for the driver are a tenfold improvement over other www.national.com 7 |
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