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ISL9208 Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL9208 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 28 page  11 FN6446.1 November 2, 2007 Charge Overcurrent Monitor (Assumes DENOCC bit is ‘0’) Serial Interface Timing Diagrams Bus Timing Symbol Table VOCC tOCC COC BIT TEMP3V VCSENSE REGISTER 1 READ OUTPUT 3.3V ‘1’ ‘0’ CFET OUTPUT µC TURNS ON CFET 12V tSU:STO tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL tF tLOW tBUF tR tDH tAA SDA (INPUT TIMING) SDA (OUTPUT TIMING) WAVEFORM INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM LOW TO HIGH WILL CHANGE FROM LOW TO HIGH MAY CHANGE FROM HIGH TO LOW WILL CHANGE FROM HIGH TO LOW DON’T CARE: CHANGES ALLOWED CHANGING: STATE NOT KNOWN N/A CENTER LINE IS HIGH IMPEDANCE WAVEFORM INPUTS OUTPUTS ISL9208 |
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