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HCTS164D Datasheet(PDF) 1 Page - Intersil Corporation |
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HCTS164D Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 8 page 1 TM HCTS164MS Radiation Hardened 8-Bit Serial-In/Parallel-Out Shift Register Pinouts 14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835, CDIP2-T14 TOP VIEW 14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835, CDFP3-F14 TOP VIEW DS1 DS2 Q0 Q1 Q2 Q3 GND VCC Q7 Q6 Q5 Q4 MR CP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 DS1 DS2 Q0 Q1 Q2 Q3 GND VCC Q7 Q6 Q5 Q4 MR CP 14 13 12 11 10 9 8 2 3 4 5 6 7 1 Features • 3 Micron Radiation Hardened CMOS SOS • Total Dose 200K RAD (Si) • Dose Rate Survivability >1012 RAD (Si)/s (20ns Pulse) • Dose Rate Upset >1010 RAD (Si)/s (20ns Pulse) • Single Event Ray Upset Rate < 2 x 10-9 Errors/Bit Day (Typ) • LET Threshold >100 MEV-cm2/mg • Latch-Up-Free Under Any Conditions • Military Temperature Range: -55oC to +125oC • Significant Power Reduction Compared to LSTTL ICs • DC Operating Voltage Range: 4.5V to 5.5V • Input Logic Levels -VIL = 0.8 VCC (Max) -VIH = VCC/2 (Min) • Input Current Levels Ii ≤5µA at VOL, VOH Description The Intersil HCTS164MS is a radiation hardened 8-bit Serial-In/ Parallel-Out Shift Register with asynchronous reset. The HCTS164MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of the radiation hardened, high-speed, CMOS/SOS Logic Family. August 1995 Ordering Information PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCTS164DMSR -55oC to +125oC Intersil Class S Equivalent 14 Lead SBDIP HCTS164KMSR -55oC to +125oC Intersil Class S Equivalent 14 Lead Ceramic Flatpack HCTS164D/Sample +25oC Sample 14 Lead SBDIP HCTS164K/Sample +25oC Sample 14 Lead Ceramic Flatpack HCTS164HMSR +25oCDie Die Truth Table OPERATING MODE INPUTS OUTPUTS MR CP DS1 † DS2 † Q0 Q1-Q7 Reset (Clear) L XXX L L-L Shift H L L L q0 -q6 HL H L q0 - q6 HH L L q0 - q6 HH H H q0 - q6 H = High Voltage Level L = Low Voltage Level = LOW-to-HIGH clock transition q = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition † = DS1 and DS2 inputs must be at state one setup prior to CP (rising edge) FN 3386.1 Spec Number 518613 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved |
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