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HD-15531 Datasheet(PDF) 6 Page - Intersil Corporation |
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HD-15531 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 16 page 6 ting the decoded data through SERIAL DATA OUT. The decoded data available at SERIAL DATA OUT is in NRZ format. The DECODER SHIFT CLOCK is provided so that the decoded bits can get shifted into an external register on every low-to-high transition of this clock - . Note that DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high. After all K decoded bits have been transmitted the data is checked for parity. A high input on DECODER PARITY SELECT will set the Decoder to check for even parity or a low input will set the Decoder to check for odd parity. A high on VALID WORD output indicates a successful reception of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approx- imately K + 4 DECODER SHIFT CLOCK periods after it goes high, if not reset low sooner by a valid sync and two valid Manchester bits as shown . At any time in the above sequence a high input on DECODER RESET during a low-to-high transition of DECODER SHIFT CLOCK will abort transmission and ini- tialize the Decoder to start looking for a new sync character. 2 3 3 4 1 SERIAL 1ST HALF TIMING SYNCHRONOUS CLOCK DECODER SHIFT CLOCK BIPOLAR ONE IN BIPOLAR ZERO IN TAKE DATA 2ND HALF SYNC SYNC MSB MSB BIT K-1 BIT K-1 BIT K-2 BIT K-2 BIT K-3 BIT K-3 BIT K-5 BIT K-4 BIT K-5 BIT K-4 01 23 45 6 7 8 N-3 N-2 N-1 N BIT 3 BIT 2 PARITY BIT 1 BIT 2 BIT 3 BIT 1 PARITY BITK-1 VALID WORD DATA SYNC COMMAND MSB BITK-2 BITK-3 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 3 4 2 1 (MAY BE HIGH FROM PREVIOUS RECEPTION) UNDEFINED DATA OUT SYNC FIGURE 2. DECODER HD-15531 |
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