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CS80C286-20 Datasheet(PDF) 6 Page - Intersil Corporation |
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CS80C286-20 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 60 page 6 Functional Description Introduction The Intersil 80C286 microprocessor is a static CMOS ver- sion of the NMOS 80286 microprocessor. The 80C286 is an advanced, high-performance microprocessor with specially optimized capabilities for multiple user and multi-tasking sys- tems. Depending on the application, the 80C286's perfor- mance is up to nineteen times faster than the standard 5MHz 8086's, while providing complete upward software compatibility with Intersil 80C86 and 80C88 CPU family. The 80C286 operates in two modes: 80C286 real address mode and protected virtual address mode. Both modes exe- cute a superset of the 80C86 and 80C88 instruction set. In 80C286 real address mode programs use real addresses with up to one megabyte of address space. Programs use vir- tual addresses in protected virtual address mode, also called protected mode. In protected mode, the 80C286 CPU automat- ically maps 1 gigabyte of virtual addresses per task into a 16 megabyte real address space. This mode also provides mem- ory protection to isolate the operating system and ensure pri- vacy of each tasks' programs and data. Both modes provide the same base instruction set, registers and addressing modes. The Functional Description describes the following: Static oper- ation, the base 80C286 architecture common to both modes, 80C286 real address mode, and finally, protected mode. Static Operation The 80C286 is comprised of completely static circuitry. Internal registers, counters, and latches are static and require no refresh as with dynamic circuit design. This elim- inates the minimum operating frequency restriction typically placed on microprocessors. The CMOS 80C286 can oper- ate from DC to the specified upper frequency limit. The clock to the processor may be stopped at any point (either phase one or phase two of the processor clock cycle) and held there indefinitely. There is, however, a significant decrease in power requirement if the clock is stopped in phase two of the processor clock cycle. Details on the clock relationships will be discussed in the Bus Operation sec- tion. The ability to stop the clock to the processor is espe- cially useful for system debug or power critical applications. RESET 29 l SYSTEM RESET: clears the internal logic of the 80C286 and is active HIGH. The 80C286 may be reinitialize at any time with a LOW to HIGH transition on RESET which remains active for more than 16 system clock cycles. During RESET active, the output pins of the 80C286 enter the state shown below. Operation of the 80C286 begins after a HlGH to LOW transition on RESET. The HIGH to LOW transition of RESET must be synchronous to the system clock. Approximately 50 system clock cycles are required by the 80C286 for internal initializations before the first bus cycle to fetch code from the power-on execution address is performed. A LOW to HIGH transition of RESET synchronous to the system clock will end a processor cycle at the second HIGH to LOW transition of the system clock. The LOW to HIGH transition of RESET may be asynchronous to the system clock; however, in this case it cannot be predetermined which phase of the processor clock will occur during the next system clock period. Synchronous LOW to HIGH transitions of RESET are required only for systems where the processor clock must be phase synchronous to another clock. VSS 9, 35, 60 l SYSTEM GROUND: are the ground pins (all must be connected to system ground). VCC 30, 62 l SYSTEM POWER: +5V power supply pins. A 0.1 μF capacitor between pins 60 and 62 is recommended. NOTES: 1. READY is an open-collector signal and should be pulled inactive with an appropriate resistor (620 Ω at 10MHz and 12.5MHz, 470Ω at 16MHz, 390 Ω at 20MHz, 270Ω at 25MHz). 2. HLDA is only Low if HOLD is inactive (Low). 3. All unused inputs should be pulled to their inactive state with pull up/down resistors. Pin Descriptions The following pin function descriptions are for the 80C286 microprocessor. (Continued) SYMBOL PIN NUMBER TYPE DESCRIPTION 80C286 PIN STATE DURING RESET PIN VALUE PIN NAMES 1 (HIGH) S0, S1, PEACK, A23 - A0, BHE, LOCK 0 (LOW) M/IO, COD/lNTA, HLDA (Note 2) HIGH IMPEDANCE D15 - D0 80C286 |
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