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L6327

L6332

February 2001

This is preliminary information on a new product now in development. Details are subject to change without notice.

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Power Supplies +5Vdc, -5Vdc

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Current bias or voltage bias (selectable) /

Differential Voltage Sense architecture

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6 or 4 channel versions

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38-pin TSSOP package (for either 6 or 4

channels)

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Internal reference Resistor for read and write

currents

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Read channel -3dB bandwidth > 400MHz

(Rmr=50 ohm no interconnect)

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Input equivalent preamplifier voltage noise

0.5nV/rtHz nominal

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Input equivalent MR bias current noise 10 pA/

rtHz nominal

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MR bias current programmable (5 bit DAC) 1.5-

7.0mA nominal MR bias voltage programmable

(5 bit DAC) 65-335mV nominal

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Programmable gain (100V/V, 150, 200 and

250V/V) and read bandwidth

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Write frequency up to 300 MHz (Lh=70nH,

Rh=20 ohms, Ch=2pF, VEE=-5V)

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Rise/Fall time 0.6ns ( Iw =40mA 0-pk, Lh=70nH,

Rh=20 ohms, Ch=2pF, VEE=-5V)

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Write current programmable (5 bit DAC) 15-60mA

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PECL write data input

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Bi-directional 16-bit TTL Serial interface for

head selection, read/write currents selection,

chip parameters modification, chip enable,

vendor code and fault status read back registers

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2-pin mode selection (R/W, MRR)

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Bank write feature for servo write

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Digital buffered head voltage DBHV / Analog

buffered head voltage ABHV pin (gain 5)

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Thermal asperity detection & correction with

adjustable sensitivity level (6 bit DAC)

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Automatic successive approximation digital

measurement of temperature and Rmr (7 bits)

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Read and write head open/short detection, low

low supply detect and temperature monitoring

(high temperature warning and Analog

Temperature Diode Voltage measurement)

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Low write frequency detection.

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WRITE to READ fast recovery 150ns (same

head, including 100ns blanking period)

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Head-to-head switch in READ mode - 10

µs (nom)

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Head and MR bias current switching transient

current head protection

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READ-to-WRITE switching 50ns (same head)

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Programmable read bias during write and bank

write operation

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ESD diode for GMR head protection

DESCRIPTION

L6327/L6332 is a BICMOS monolithic integrated cir-

cuit GMR differential preamplifier designed for use

with four-terminal magneto-resistive GMR read/in-

ductive write heads. It is available as either a six

(L6327) or four (L6332) channel device. The devices

consist of a voltage-sense, current-bias or voltage-

bias (selectable), differential input and differential

output, low-noise, high bandwidth read amplifier and

include fast current switching write drivers which sup-

port data rates in excess of 550 Mb/s with 70nH write

heads.

The GMR preamplifier provides programmable read

current / voltage bias and write current (5 bit DAC for

the read bias, 5 bit DAC for the write current), fault

detection circuitry and servo writing features. Read

amplifier gain, write current wave shape (overshoot,

undershoot and damping) can be adjusted and a

thermal asperity detection and correction circuit can

be enabled and programmed with different thresh-

olds (6 bit DAC) through a 16-bit bi-directional serial

interface (SDEN, SDATA, SCLK). The device oper-

ates from a +5V supply and a -5V supply (nominal).

No external components are required as a trimmed

or untrimmed resistor for reference current setting is

employed.

TSSOP38

ORDERING NUMBERS: L6327

L6332

PRODUCT PREVIEW

6 / 4 CHANNEL VOLTAGE SENSE GMR PREAMPLIFIER