W311

Rev 1.0, November 25, 2006

Page 5 of 18

W311 Serial Configuration Map

1. The serial bits will be read by the clock driver in the following

order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

2. All unused register bits (reserved and N/A) should be

written to a “0” level.

3. All register bits labeled “Initialize to 0" must be written to

zero during initialization.

Byte 0: Control Register 0

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

0

Reserved

Bit 6

–

SEL2

0

See

Table 5

Bit 5

–

SEL1

0

See

Table 5

Bit 4

–

SEL0

0

See

Table 5

Bit 3

–

FS_Override

0

0 = Select operating frequency by FS[4:0] input pins

1 = Select operating frequency by SEL[4:0] settings

Bit 2

–

SEL4

1

See

Table 5

Bit 1

–

SEL3

0

See

Table 5

Bit 0

–

Reserved

0

Reserved

Byte 1: Control Register 1

Bit

Pin#

Name

Default

Description

Bit 7

-

Reserved

0

Reserved

Bit 6

-

Spread Select2

0

‘000’ = Normal (spread off)

‘001’ = Test Mode

‘010’ = Reserved

‘011’ = Three-Stated

‘100’ = –0.5%

‘101’ = ± 0.5%

‘110’ = ± 0.25%

‘111’ = ± 0.38%

Bit 5

-

Spread Select1

0

Bit 4

-

Spread Select0

0

Bit 3

35

CPU3

1

(Active/Inactive)

Bit 2

38

CPU2

1

(Active/Inactive)

Bit 1

39

CPU1

1

(Active/Inactive)

Bit 0

42

APIC2

1

(Active/Inactive)

Byte 2: Control Register 2

Bit

Pin#

Name

Default

Description

Bit 7

20

PC8

1

(Active/Inactive)

Bit 6

18

PCI7

1

(Active/Inactive)

Bit 5

17

PCI6

1

(Active/Inactive)

Bit 4

16

PCI5

1

(Active/Inactive)

Bit 3

14

PCI4

1

(Active/Inactive)

Bit 2

13

PCI3

1

(Active/Inactive)

Bit 1

11

PCI2

1

(Active/Inactive)

Bit 0

10

PCI1

1

(Active/Inactive)