CY28437

Rev 1.0, November 20, 2006

Page 8 of 22

Byte 8: Control Register 8

Bit

@Pup

Name

Description

7

0

CPU_SS

Spread Selection for CPU PLL

0: –0.5% (peak to peak)

1: –1.0% (peak to peak)

6

0

CPU_DWN_SS

Spread Selection for CPU PLL

0: Down spread

1: Center spread

5

0

SRC_SS_OFF

SRC Spread Spectrum Enable

0 = Spread off, 1 = Spread on

4

0

SRC_SS

Spread Selection for SRC PLL

0: –0.5% (peak to peak)

1: –1.0% (peak to peak)

3

0

RESERVED

RESERVED, Set = 0

2

1

USB

48-MHz Output Drive Strength

0 = 2x, 1 = 1x

1

1

PCI

33-MHz Output Drive Strength

0 = 2x, 1 = 1x

0

0

RESERVED

RESERVED, Set = 0

Byte 9: Control Register 9

Bit

@Pup

Name

Description

7

0

DF_Limit2

Dynamic Frequency Max threshold. These three bits will set the max

allowed CPU frequency for Dynamic Frequency

6

0

DF_Limit1

5

0

DF_Limit0

4

0

DF_EN

Dynamic Frequency Enable

0 = Disable, 1 = Enable

3

0

FSEL_D

SW Frequency selection bits. See Table 1.

20

FSEL_C

1

0

FSEL_B

0

0

FSEL_A

Byte 10: Control Register 10

Bit

@Pup

Name

Description

7

0

Recovery_Frequency

This bit allows selection of the frequency setting that the clock will be

restored to once the system is rebooted

0: Use HW settings, 1: Recovery N[8:0]

6

0

Timer_SEL

Timer_SEL selects the WD reset function at SRESET pin when WD time

out.

0 = Reset and Reload Recovery_Frequency

1 = Only Reset

5

1

Time_Scale

Time_Scale allows selection of WD time scale

0 = 294 ms

1 = 2.34 s

4

0

WD_Alarm

WD_Alarm is set to “1” when the watchdog times out. It is reset to “0” when

the system clears the WD_TIMER time stamp.

3

0

WD_TIMER2

Watchdog timer time stamp selection

000: Reserved (test mode)

001: 1 * Time_Scale

010: 2 * Time_Scale

011: 3 * Time_Scale

100: 4 * Time_Scale

101: 5 * Time_Scale

110: 6 * Time_Scale

111: 7 * Time_Scale

20

WD_TIMER1

10

WD_TIMER0