 |
 |
|
| CY28439 |
|
|||||||||||||||||
 SPECTRALINEAR
|
| |||||||||||||||||
|
2 page 
CY28439 Rev 1.0, November 21, 2006 Page 2 of 21 Pin Description Pin No. Name Type Description 6,56 VDD_PCI PWR 3.3V power supply for outputs. 1,5 VSS_PCI GND Ground for outputs. 3 FS_E/PCI4 I,O, PU,SE 3.3V-tolerant input for CPU frequency selection/33-MHz clock. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 2,4,53,54, 55 PCI O, SE 33-MHz clocks. 7PCIF0 O,SE 33-MHz free running clock 8 FS_A/PCIF1 I/O,PD, SE 3.3V-tolerant input for CPU frequency selection/Free running 33-MHz clock. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 9 FS_B/PCIF2 I/O,PU, SE 3.3V-tolerant input for CPU frequency selection/Free running 33-MHz clock. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 16 VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C,FS_D, FS_E, SEL24_48. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power down (active HIGH). 10 VDD_48 PWR 3.3V power supply for outputs. 11 SEL24_48#/24_48 M I/O, PD, SE Latched select input for 24-/48-MHz output/ 24-/48-MHz output 0 = 48 MHz, 1 = 24 MHz 12 USB48 I/O, 48-MHz clock output. 13 VSS_48 GND Ground for outputs. 14,15 DOT96T, DOT96C O, DIF Fixed 96-MHz clock output. 17,18,21, 22,23,24, 30,31,32, 33 SRCT/C O, DIF Differential serial reference clocks. Outputs have overclocking capability. 19,28,34 VDD_SRC PWR 3.3V power supply for outputs. 26,27 SRCT/C_SATAT/C O, DIF Differential serial reference clock. Recommended output for SATA. 20,25,29 VSS_SRC GND Ground for outputs. 35 VDDA PWR 3.3V power supply for PLL. 36 VSSA GND Ground for PLL. 37 IREF I A precision resistor is attached to this pin, which is connected to the internal current reference. 41 VDD_CPU PWR 3.3V power supply for outputs. 39,40,42,43 CPUT/C O, DIF Differential CPU clock outputs. 38 VSS_CPU GND Ground for outputs. 45 SCLK I SMBus-compatible SCLOCK. 44 SDATA I/O SMBus-compatible SDATA. 46 VDD_REF PWR 3.3V power supply for outputs. 47 XOUT O, SE 14.318-MHz crystal output. 48 XIN I 14.318-MHz crystal input. 49 VSS_REF GND Ground for outputs. 50 REF0/FS_D I/O, SE, PD 3.3V-tolerant input for CPU frequency selection/Reference clock. Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications. 51 REF1/FS_C O, SE, PD 3.3V-tolerant input for CPU frequency selection/Reference clock. Selects test mode if pulled to VIHFS_C when VTT_PWRGD# is asserted low. Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifica- tions. 52 SRESET# O, SE 3.3V output for Watchdog reset. This output is open drain type with a high (>100-k ) internal pull-up resistor. |
