CY28416

Rev 1.0, November 22, 2006

Page 2 of 14

Pin Definition

Pin No.

Name

Type

Description

47,46,44,43

CPUT/C[0:1]

O, DIF Differential CPU clock output.

39,38

CPUT2_ITP/SRCT4

CPUC2_ITP/SRCC4

O, DIF Selectable Differential CPU or SRC clock output.

ITP_EN = 0 @VTT_PWRGD# assertion PIN 39,38 = SRCT4,SRCC4

ITP_EN = 1 @VTT_PWRGD# assertion PIN 39,38 = CPUT2_ITP,CPUC2_ITP

23,24

DOT96T, DOT96C

O, DIF Differential 96 MHz clock output.

6

FS_A/REF1

I/O, SE 3.3V tolerant input for CPU frequency/REF clock

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications

.

20

FS_B/48 MHz0

I/O, SE 3.3V tolerant input for CPU frequency/48 MHz clock

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications

.

7

FS_C/REF0

I

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications

.

42

IREF

I

A precision resistor is attached to this pin, which is connected to the internal

current reference.

18

ITP_EN/PCIF1

I/O, SE Enable SRC4 or CPU2_ITP/PCIF clock.

(sampled on the VTT_PWRGD# assertion). 0 = SRC4, 1 = CPU2_ITP

9,10,13,14

PCI

O, SE 33 MHz clock output.

21

48 MHz1

O, SE 48 MHz clock output. (Uses same control SMBus register as 48 MHz0 to control

enable/disable.)

1

SCLK

I

SMBus compatible SCLOCK.

2

SDATA

I/O

SMBus compatible SDATA.

26,27,29,30,

34,35

SRCT/C[0:3]

O, DIF Differential Serial reference clock.

31,32

SRCT2_SATA,

SRCC2_SATA

O, DIF Differential Serial reference clock. Recommended output for SATA

17

TEST_SEL/PCIF0

I/O, SE,

PD

LVTTL input for selecting HI-Z or Normal operation/33 MHz Clock

0 = Normal operation, 1 = HI-Z when VTT_PWRGD# is sampled

19

VDD_48

PWR

3.3V power supply for outputs

45

VDD_CPU

PWR

3.3V power supply for outputs

11, 16

VDD_PCI

PWR

3.3V power supply for outputs

8

VDD_REF

PWR

3.3V power supply for outputs

33, 37

VDD_SRC

PWR

3.3V power supply for outputs

40

VDDA

PWR

3.3V power supply for PLL

22

VSS_48

GND

Ground for outputs

48

VSS_CPU

GND

Ground for outputs

12, 15

VSS_PCI

GND

Ground for outputs

5

VSS_REF

GND

Ground for outputs

28, 36

VSS_SRC

GND

Ground for outputs

41

VSSA

GND

Ground for PLL

25

VTT_PWRGD#/PD

I, PD

3.3V LVTTL Input. This pin is a level-sensitive strobe used to latch the FS_A,

FS_B, FS_C/TEST_SEL, and PCIF0/ITP_EN Inputs. After asserting

VTT_PWRGD# (active LOW), this pin becomes a realtime input for asserting

power-down (active HIGH)

4

XIN

I

14.318 MHz Crystal Input

3

XOUT

O

14.318 MHz Crystal Output