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CY28409OXC Datasheet(PDF) 5 Page - SpectraLinear Inc |
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CY28409OXC Datasheet(HTML) 5 Page - SpectraLinear Inc |
5 / 16 page CY28409 Rev 1.0, November 22, 2006 Page 5 of 16 3 Externally Selected PCI_STP# PCI_STP# reflects the current value of the external PCI_STP# pin. 0 = PCI_STP# pin is LOW. 2 Externally Selected CPU_STP# CPU_STP# reflects the current value of the external CPU_STP# pin. 0 = CPU_STP# pin is LOW. 1 Externally Selected FS_B FS_B reflects the value of the FS_B pin sampled on power-up. 0 Externally Selected FS_A FS_A reflects the value of the FS_A pin sampled on power-up. Byte 1: Control Register 1 Bit @Pup Name Description 7 0 SRCT, SRCC Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP 0 = Free Running, 1 = Stopped with PCI_STP# 6 1 SRCT, SRCC SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled 5 1 Reserved Reserved, Set = 1 4 1 Reserved Reserved, Set = 1 3 1 Reserved Reserved, Set = 1 2 1 CPUT2, CPUC2 CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled 1 1 CPUT1, CPUC1 CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled 0 1 CPUT0, CPUC0 CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled Byte 2: Control Register 2 Bit @Pup Name Description 7 0 SRCT, SRCC SRCT/C Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down 6 0 SRCT, SRCC SRCT/C Stop Drive Mode 0 = Driven during PCI_STP, 1 = Three-state during PCI_STP 5 0 CPUT2, CPUC2 CPUT/C2 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down 4 0 CPUT1, CPUC1 CPUT/C1 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down 3 0 CPUT0, CPUC0 CPUT/C0 Pwrdwn Drive Mode 0 = Driven during power-down, 1 = Three-state during power-down 2 0 CPUT2, CPUC2 CPUT/C2 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped 1 0 CPUT1, CPUC1 CPUT/C1 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped 0 0 CPUT0, CPUC0 CPUT/C0 stop Drive Mode 0 = Driven when stopped, 1 = Three-state when stopped Byte 3: Control Register 3 Bit @Pup Name Description 7 1 SW PCI STOP SW PCI_STP Function 0= PCI_STP assert, 1= PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will resume in a synchronous manner with no short pulses. 6 1 PCI6 PCI6 Output Enable 0 = Disabled, 1 = Enabled Byte 0:Control Register 0 (continued) Bit @Pup Name Description |
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