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CY28405OC-3 Datasheet(PDF) 6 Page - SpectraLinear Inc |
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CY28405OC-3 Datasheet(HTML) 6 Page - SpectraLinear Inc |
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6 / 16 page  CY28405-3 Rev 1.0, November 22, 2006 Page 6 of 16 Byte 4: Control Register Bit @Pup Name Description 7 0 USB_48 USB_48MHz Drive Strength Control 0 = Low Drive Strength, 1 = High Drive Strength 6 1 USB_48 USB_48MHz Output Enable 0 = Disabled, 1 = Enabled 5 0 PCIF2 Allow control of PCIF2 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP 4 0 PCIF1 Allow control of PCIF1 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP 3 0 PCIF0 Allow control of PCIF0 with assertion of SW PCI_STP 0 = Free Running, 1 = Stopped with SW PCI_STP 2 1 PCIF2 PCIF2 Output Enable 0 = Disabled, 1 = Enabled 1 1 PCIF1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled 0 1 PCIF0 PCIF0 Output Enable 0 = Disabled, 1 = Enabled Byte 5: Control Register Bit @Pup Name Description 7 1 DOT_48 DOT_48MHz Output Enable 0 = Disabled, 1 = Enabled 6 1 Reserved Reserved 5 0 3V66_3/VCH 3V66_3/VCH Frequency Select 0 = 3V66 mode, 1 = VCH (48MHz) mode 4 1 3V66_3/VCH 3V66_3/VCH Output Enable 0 = Disabled, 1 = Enabled 3 1 Reserved Reserved, set = 1 2 1 3V66_2 3V66_2 Output Enable 0 = Disabled, 1 = Enabled 1 1 3V66_1 3V66_1 Output Enable 0 = Disabled, 1 = Enabled 0 1 3V66_0 3V66_0 Output Enable 0 = Disabled, 1 = Enabled Byte 6: Control Register Bit @Pup Name Description 7 0 Reserved Reserved, set = 0 6 0 Reserved Reserved, set = 0 5 0 CPUC0, CPUT0 CPUC1, CPUT1 CPUT_ITP,CPUC_ITP FS_A & FS_B Operation 0 = Normal, 1 = Test mode 4 0 SRCT, SRCC SRCT/C Frequency Select 0 = 100Mhz, 1 = 200MHz 30 PCIF PCI 3V66 SRCT,SRCC CPUT_ITP,CPUC_ITP Spread Spectrum Mode 0 = down (default), 1 = center |
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Similar Description - CY28405OC-3 |
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