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CY28404OXCT Datasheet(PDF) 4 Page - SpectraLinear Inc |
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CY28404OXCT Datasheet(HTML) 4 Page - SpectraLinear Inc |
4 / 19 page CY28404 Rev 1.0, November 22, 2006 Page 4 of 19 Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. The interface can also be accessed during power down operation. Data Protocol The clock driver serial protocol accepts Byte Write, Byte Read, Block Write and Block Read operation from any external I2C controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. The Block Write and Block Read protocol is outlined in Table 4 while Table 5 outlines the corresponding Byte Write and Byte Read protocol.The slave receiver address is 11010010 (D2h). Table 3. Command Code Definition Bit Description 7 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation (6:0) Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be ‘0000000’ Table 4. Block Read and Block Write protocol Block Write Protocol Block Read Protocol Bit Description Bit Description 1Start 1Start 2:8 Slave address – 7 bits 2:8 Slave address – 7 bits 9Write 9Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code – 8-bit ‘00000000’ stands for block operation 11:18 Command Code – 8-bit ‘00000000’ stands for block operation 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Byte Count – 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address – 7 bits 29:36 Data byte 0 – 8 bits 28 Read 37 Acknowledge from slave 29 Acknowledge from slave 38:45 Data byte 1 – 8 bits 30:37 Byte count from slave – 8 bits 46 Acknowledge from slave 38 Acknowledge .... Data Byte N/Slave Acknowledge... 39:46 Data byte from slave – 8 bits .... Data Byte N – 8 bits 47 Acknowledge .... Acknowledge from slave 48:55 Data byte from slave – 8 bits .... Stop 56 Acknowledge .... Data bytes from slave/Acknowledge .... Data byte N from slave – 8 bits .... Not Acknowledge .... Stop |
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