CY28405-2 datasheet(5/48 Pages) SPECTRALINEAR

Part #	CY28405-2

Description	Clock Synthesizer with Differential SRC and CPU Outputs

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Manufacturer	SPECTRALINEAR [SpectraLinear Inc]

Direct Link	http://www.spectralinear.com

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5 / 48 page

CY28405-2

Rev 1.0, November 22, 2006

Page 5 of 16

Byte 1: Control Register

Bit

@Pup

Name

Description

7

0

SRCT

SRCC

Allow control of SRC during SW PCI_STP assertion

0 = Free Running, 1 = Stopped with SW PCI_STP

6

1

SRCT

SRCC

SRC Output Enable

0 = Disabled (three-state), 1 = Enabled

5

1

Reserved

Reserved, set = 1

4

1

Reserved

Reserved, set = 1

3

1

Reserved

Reserved, set = 1

2

1

CPUT_ITP, CPUC_ITP

CPU_ITP Output Enable

0 = Disabled (three-state), 1 = Enabled

1

CPUT1, CPUC1

CPU(T/C)1 Output Enable,

0 = Disabled (three-state), 1 = Enabled

0

1

CPUT0, CPUC0

CPUT/C)0 Output Enable

0 = Disabled (three-state), 1 = Enabled

Byte 2: Control Register

Bit

@Pup

Name

Description

7

0

SRCT, SRCC

SRCT/C Pwrdwn drive mode

0 = Driven in power-down, 1 = three-state in power-down

6

0

SRCT, SRCC

SRC Stop drive mode

0 = Driven in PCI_STP, 1 = three-state in power-down

5

0

CPUT_ITP, CPUC_ITP

CPU(T/C)_ITP Pwrdwn drive mode

0 = Driven in power-down, 1 = three-state in power-down

4

0

CPUT1, CPUC1

CPU(T/C)1 Pwrdwn drive mode

0 = Driven in power-down, 1 = three-state in power-down

3

0

CPUT0, CPUC0

CPU(T/C)0 Pwrdwn drive mode

0 = Driven in power-down, 1 = three-state in power-down

2

0

Reserved

Reserved, set = 0

1

0

Reserved

Reserved, set = 0

0

Reserved

Reserved, set = 0

Byte 3: Control Register

Bit

@Pup

Name

Description

7

1

SW PCI STOP

SW PCI_STP Function

0= PCI_STP assert, 1= PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will

be stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will

resume in a synchronous manner with no short pulses.

6

1

Reserved

5

1

PCI5

PCI5 Output Enable

0 = Disabled, 1 = Enabled

4

1

PCI4

PCI4 Output Enable

0 = Disabled, 1 = Enabled

3

1

PCI3

PCI3 Output Enable

0 = Disabled, 1 = Enabled

2

1

PCI2

PCI2 Output Enable

0 = Disabled, 1 = Enabled

1

PCI1

PCI1 Output Enable

0 = Disabled, 1 = Enabled

0

1

PCI0

PCI0 Output Enable

0 = Disabled, 1 = Enabled

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