CY28404

Rev 1.0, November 22, 2006

Page 2 of 19

Pin Description

Pin No.

Name

Type

Description

1, 2, 48

REF(0:2)

O, SE

Reference Clock. 3.3V 14.318 MHz clock output.

1, 2, 7, 8, 9

FS_A, FS_B, FS_C,

FS_D, FS_E

I

3.3V LVTTL Latched Input for CPU Frequency Selection.

4XIN

I

Crystal Connection or External Reference Frequency Input. This pin has

dual functions. It can be used as an external 14.318 MHz crystal connection or

as an external reference frequency input.

5

XOUT

O, SE

Crystal Connection. Connection for an external 14.318 MHz crystal output.

40, 43

CPUT(0:1)

O, DIF

CPU Clock Output. Differential CPU clock outputs.

39, 42

CPUC(0:1)

O, DIF

CPU Clock Output. Differential CPU clock outputs.

37, 36

DNC

Do Not Connect

30, 31

3V66(0:1)

O, SE

66 MHz Clock Output. 3.3V 66 MHz clock from internal VCO.

26

3V66_3/VCH/

SELVCH

I/O, SE

PD

48 or 66 MHz Clock Output. 3.3V selectable through external SELVCH

strapping resistor and SMBus to be 66 MHz or 48 MHz. Default is 66 MHz.

0 = 66 MHz, 1 = 48 MHz

27

3V66_2/MODE

I/O, SE

PU

66 MHz Clock Output. 3.3V 66 MHz clock from internal VCO. Reset or

Power-down Mode Select. Selects between RESET# output or PWRDWN#

input for the PWRDWN#/RESET# pin. Default is RESET#. 0 = PD, 1 = RESET.

7, 8, 9

PCI_F(0:2)

O, SE,PU Free Running PCI Output. 33 MHz clocks divided down from 3V66.

12, 13, 14, 15,

18, 19

PCI(0:5)

O, SE

PCI Clock Output. 33 MHz clocks divided down from 3V66.

23

USB_48

O, SE

Fixed 48 MHz Clock Output.

22

DOT_48

O, SE

Fixed 48 MHz Clock Output.

45

IREF

I

Current Reference. A precision resistor is attached to this pin which is

connected to the internal current reference.

20

RESET#/PD#

I/O, PU

3.3V LVTTL Input for PowerDown# active LOW. Watchdog Time-out Reset

Output.

21

SEL24#/

24_48MHz

I/O, SE

PU

24 or 48 MHz Output. 3.3V fixed 24 MHz or 48 MHz non-spread spectrum

output selectable through an external power-on strapping resistor tied to this

pin. 0 = 24 MHz, 1 = 48 MHz

34

VTT_PWRGD#

I

3.3V LVTTL Input is a Level Sensitive Strobe used to Latch the FS[A:E]

Input (active LOW).

33

SDATA

I/O

SMBus-compatible SDATA.

32

SCLK

I

SMBus-compatible SCLOCK.

47

VDDA

PWR

3.3V Power Supply for PLL.

46

VSSA

GND

Ground for PLL.

3, 10, 16, 25,

28, 35, 41

VDD(REF,PCI,48,3

V66,CPU),

PWR

3.3V Power Supply for Outputs.

6, 11, 17, 29,

38, 44, 46

VSS(REF,PCI,48,3V

66,CPU,ITP)

GND

Ground for Outputs.