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CY28401OXC Datasheet(PDF) 6 Page - SpectraLinear Inc |
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CY28401OXC Datasheet(HTML) 6 Page - SpectraLinear Inc |
6 / 13 page CY28401 Rev 1.0, November 21, 2006 Page 6 of 13 PWRDWN# Clarification[1] The PWRDWN# pin is used to shut off all clocks cleanly and instruct the device to evoke power savings mode. Additionally, PWRDWN# should be asserted prior to shutting off the input clock or power to ensure all clocks shut down in a glitch-free manner. PWRDWN# is an asynchronous active LOW input. This signal is synchronized internal to the device prior to powering down the clock buffer. PWRDWN# is an asynchronous input for powering up the system. When PWRDWN# is asserted LOW, all clocks will be held HIGH or three-stated (depending on the state of the control register drive mode and OE bits) prior to turning off the VCO. All clocks will start and stop without any abnormal behavior and must meet all AC and DC parameters. This means no glitches, frequency shifting or amplitude abnormalities among others. PWRDWN# Assertion When PWRDWN# is sampled LOW by two consecutive rising edges of DIFC, all DIFT outputs will be held HIGH or three-stated (depending on the state of the control register drive mode and OE bits) on the next DIFC HIGH-to-LOW transition. When the SMBus power-down drive mode bit is programmed to ‘0’, all clock outputs will be held with the DIFT pin driven high at 2 x Iref and DIFC three-state. However, if the control register PWRDWN# drive mode bit is programmed to ‘1’, then both DIFT and the DIFC are three-stated. PWRDWN# Deassertion The power-up latency is less than 1 ms. This is the time from the deassertion of the PWRDWN# pin or the ramping of the power supply or the time from valid SRC_IN input clocks until the time that stable clocks are output from the buffer chip (PLL locked). If the control register PWRDWN# three-state bit is programmed to ‘1’, all differential outputs must be driven high in less than 300 s of PWRDWN# deassertion to a voltage greater than 200 mV. Notes: 1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches excessive frequency shifting. 2. The total power-up latency from power on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input). 3. Lock output is a latched signal that is reset with the assertion of PWRDWN# or when VDD < 1.8V, 4. Special care must be taken to ensure that no abnormal clock behavior occurs after the assertion PLL LOCK (i.e., overshoot undershoot is allowed). 5. If power is valid and PWRDWN# is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks are detected, valid power, PWRDWN# deasserted with the PLL locked and stable are the DIF outputs enabled. Table 4. Buffer Power-up State Machine State Description 0 3.3V Buffer power off 1 After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay 2[5] Buffer waits for a valid clock on the SRC_IN input and PWRDWN# deassertion 3[2,3,4] Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation PWRDWN# DIFC DIFT Figure 1. PWRDWN# Assertion Diagram DIFC DIFT Tstable <1mS PWRDWN# Tdrive_Pwrdwn# <300uS, >200mV Figure 2. PWRDWN# Deassertion Diagram |
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