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 SPECTRALINEAR
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5 page 
CY28400 Rev 1.0, November 21, 2006 Page 5 of 12 PWRDWN# Clarification[1] The PWRDWN# pin is used to shut off all clocks cleanly and instruct the device to evoke power savings mode. Additionally, PWRDWN# should be asserted prior to shutting off the input clock or power to ensure all clocks shut down in a glitch-free manner. PWRDWN# is an asynchronous active LOW input. This signal is synchronized internal to the device prior to powering down the clock buffer. PWRDWN# is an asynchronous input for powering up the system. When PWRDWN# is asserted LOW, all clocks will be held HIGH or three-stated (depending on the state of the control register drive mode and OE bits) prior to turning off the VCO. All clocks will start and stop without any abnormal behavior and must meet all AC and DC parameters. This means no glitches, frequency shifting or amplitude abnormalities among others. PWRDWN# Assertion When PWRDWN# is sampled LOW by two consecutive rising edges of DIFC, all DIFT outputs will be held HIGH or three-stated (depending on the state of the control register drive mode and OE bits) on the next DIFC HIGH-to-LOW transition. When the SMBus power-down drive mode bit is programmed to ‘0’, all clock outputs will be held with the DIFT pin driven HIGH at 2 x Iref and DIFC three-state. However, if the control register PWRDWN# drive mode bit is programmed to ‘1’, then both DIFT and the DIFC are three-stated. Note: 1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN# is an undefined mode and not recommended. Operation in this mode may result in glitches excessive frequency shifting. Byte 4: Vendor ID Register Bit @Pup Name Description 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 5 0 Revision Code Bit 1 4 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Byte 5: Control Register 5 Bit @Pup Name Description 70 Reserved 60 Reserved 50 Reserved 40 Reserved 30 Reserved 20 Reserved 10 Reserved 00 Reserved PWRDWN# DIFC DIFT Figure 1. PWRDWN# Assertion Diagram |
