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CY28372OXCT Datasheet(PDF) 8 Page - SpectraLinear Inc |
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CY28372OXCT Datasheet(HTML) 8 Page - SpectraLinear Inc |
8 / 17 page CY28372 Rev 1.0, November 20, 2006 Page 8 of 17 Byte 12 Bit @Pup Name Description Bit 7 0 REF_2 REF_2 Output Control (default: off) Bit 6 0 Reserved Reserved Bit 5 0 Reserved Reserved Bit 4 0 DARAG2 Dial-a-Ratio AGP[0:1]. Programming these bits allow modifying the frequency ratio of the AGP(1:0), PCI(5:0) and PCIF(0:1) clocks relative to the VCO. (the ratio of AGP to PCI is retained at 2:1) DARAG[2:0] VC0/AGP Ratio 000 - (Frequency Selection Default) 001 6 010 8 011 9 100 10 101 12 110 12 111 12 Bit 3 0 DARAG1 Bit 2 0 DARAG0 Bit 1 0 Fixed_PCI_SEL PCI output frequency select mode (valid only when Fixed_3V66_SEL = 1) 0 = Use Frequency Selection Table settings 1 = Use Fractional Aligner settings (default) Bit 0 0 Fixed_3V66_SEL 3V66 and PCI output frequency select mode 0 = Use Frequency Selection Table settings (default) 1 = Use Fractional Aligner settings Byte 13 Bit @Pup Name Description Bit 7 0 Reserved Reserved Bit 6 0 N6 (MSB) Dial-a-Frequency® Control Register N. These bits are for programming the PLL’s internal N register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock. (should be written together with Control Register R) Bit 5 0 N5 Bit 4 0 N4 Bit 3 0 N3 Bit 2 0 N2 Bit 1 0 N1 Bit 0 0 N0 (LSB) Byte 14 Bit @Pup Name Pin Description Bit 7 0 Reserved Reserved Bit 6 0 R5 (MSB) Dial-a-Frequency Control Register R These bits are for programming the PLL’s internal R register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock. (should be written together with Control Register N) Bit 5 0 R4 Bit 4 0 R3 Bit 3 0 R2 Bit 2 0 R1 Bit 1 0 R0 (LSB) Bit 0 0 R & N Select R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from the DAF registers into R and N. |
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